fpga_manager_streaming

         Per-Master Security bit for fpga_manager_streaming
      
Module Instance Base Address Register Address
noc_fw_l4_sys_l4_sys_scr 0xFFD13100 0xFFD13174

Offset: 0x74

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ahb_ap

RW 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dma

RW 0x0

Reserved

mpu_m0

RW 0x0

fpga_manager_streaming Fields

Bit Name Description Access Reset
24 ahb_ap
Security bit configuration for transactions from ahb_ap to fpga_manager_streaming. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
RW 0x0
8 dma
Security bit configuration for transactions from dma to fpga_manager_streaming. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
RW 0x0
0 mpu_m0
Security bit configuration for transactions from mpu_m0 to fpga_manager_streaming. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
RW 0x0