emac0tx_ecc

         Per-Master Security bit for emac0tx_ecc

Module Instance	Base Address	Register Address
`noc_fw_l4_sys_l4_sys_scr`	`0xFFD13100`	`0xFFD13110`

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`							`ahb_ap` `RW 0x0`	`Reserved`							`fpga2soc` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`mpu_m0` `RW 0x0`

emac0tx_ecc Fields

Bit	Name	Description	Access	Reset
24	`ahb_ap`	Security bit configuration for transactions from ahb_ap to emac0tx_ecc. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.	`RW`	`0x0`
16	`fpga2soc`	Security bit configuration for transactions from fpga2soc to emac0tx_ecc. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.	`RW`	`0x0`
0	`mpu_m0`	Security bit configuration for transactions from mpu_m0 to emac0tx_ecc. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

ahb_ap

Security bit configuration for transactions from ahb_ap to emac0tx_ecc. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.

RW

0x0

fpga2soc

Security bit configuration for transactions from fpga2soc to emac0tx_ecc. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.

RW

0x0

mpu_m0

Security bit configuration for transactions from mpu_m0 to emac0tx_ecc. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.

RW

0x0