uart Summary

Module Instance	Base Address
`i_uart_0_uart`	`0xFFC02000`
`i_uart_1_uart`	`0xFFC02100`

Register Address Offset	Bit Fields
`i_uart_0_uart`
`rbr_thr_dll` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_rbr_thr_dll_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_rbr_thr_dll_31to8` `RO 0x0`								`value` `RW 0x0`
`ier_dlh` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ier_dlh_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ier_dlh_31to8` `RO 0x0`								`ptime_dlh7` `RW 0x0`	`dlh6` `RW 0x0`	`dlh5` `RW 0x0`	`dlh4` `RW 0x0`	`edssi_dhl3` `RW 0x0`	`elsi_dhl2` `RW 0x0`	`etbei_dlhl` `RW 0x0`	`erbfi_dlh0` `RW 0x0`
`iir` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_iir_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_iir_31to8` `RO 0x0`								`fifoen` `RO 0x0`		`rsvd_iir_5to4` `RO 0x0`		`id` `RO 0x1`
`fcr` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rt` `WO 0x0`		`tet` `WO 0x0`		`dmam` `WO 0x0`	`xfifor` `WO 0x0`	`rfifor` `WO 0x0`	`fifoe` `WO 0x0`
`lcr` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_lcr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_lcr_31to8` `RO 0x0`								`dlab` `RW 0x0`	`break` `RW 0x0`	`sp` `RW 0x0`	`eps` `RW 0x0`	`pen` `RW 0x0`	`stop` `RW 0x0`	`dls` `RW 0x0`
`mcr` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_mcr_31to7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_mcr_31to7` `RO 0x0`									`sire` `RO 0x0`	`afce` `RW 0x0`	`loopback` `RW 0x0`	`out2` `RW 0x0`	`out1` `RW 0x0`	`rts` `RW 0x0`	`dtr` `RW 0x0`
`lsr` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_lsr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_lsr_31to8` `RO 0x0`								`rfe` `RO 0x0`	`temt` `RO 0x1`	`thre` `RO 0x1`	`bi` `RO 0x0`	`fe` `RO 0x0`	`pe` `RO 0x0`	`oe` `RO 0x0`	`dr` `RO 0x0`
`msr` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_msc_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_msc_31to8` `RO 0x0`								`dcd` `RO 0x0`	`ri` `RO 0x0`	`dsr` `RO 0x0`	`cts` `RO 0x0`	`ddcd` `RO 0x0`	`teri` `RO 0x0`	`ddsr` `RO 0x0`	`dcts` `RO 0x0`
`scr` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_scr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_scr_31to8` `RO 0x0`								`scr` `RW 0x0`
`srbr_sthr_0` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_0_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_0_31to8` `RO 0x0`								`srbr_sthr_0` `RO 0x0`
`srbr_sthr_1` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_1_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_1_31to8` `RO 0x0`								`srbr_sthr_1` `RO 0x0`
`srbr_sthr_2` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_2_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_2_31to8` `RO 0x0`								`srbr_sthr_2` `RO 0x0`
`srbr_sthr_3` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_3_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_3_31to8` `RO 0x0`								`srbr_sthr_3` `RO 0x0`
`srbr_sthr_4` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_4_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_4_31to8` `RO 0x0`								`srbr_sthr_4` `RO 0x0`
`srbr_sthr_5` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_5_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_5_31to8` `RO 0x0`								`srbr_sthr_5` `RO 0x0`
`srbr_sthr_6` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_6_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_6_31to8` `RO 0x0`								`srbr_sthr_6` `RO 0x0`
`srbr_sthr_7` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_7_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_7_31to8` `RO 0x0`								`srbr_sthr_7` `RO 0x0`
`srbr_sthr_8` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_8_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_8_31to8` `RO 0x0`								`srbr_sthr_8` `RO 0x0`
`srbr_sthr_9` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_9_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_9_31to8` `RO 0x0`								`srbr_sthr_9` `RO 0x0`
`srbr_sthr_10` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_10_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_10_31to8` `RO 0x0`								`srbr_sthr_10` `RO 0x0`
`srbr_sthr_11` `0x5C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_11_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_11_31to8` `RO 0x0`								`srbr_sthr_11` `RO 0x0`
`srbr_sthr_12` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_12_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_12_31to8` `RO 0x0`								`srbr_sthr_12` `RO 0x0`
`srbr_sthr_13` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_13_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_13_31to8` `RO 0x0`								`srbr_sthr_13` `RO 0x0`
`srbr_sthr_14` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_14_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_14_31to8` `RO 0x0`								`srbr_sthr_14` `RO 0x0`
`srbr_sthr_15` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_15_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_15_31to8` `RO 0x0`								`srbr_sthr_15` `RO 0x0`
`far` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_far_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_far_31to1` `RO 0x0`															`srbr_sthr` `RW 0x0`
`tfr` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_tfr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_tfr_31to8` `RO 0x0`								`tfr` `RO 0x0`
`rfw` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_rfw_31to10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_rfw_31to10` `RO 0x0`						`rffe` `WO 0x0`	`rfpe` `WO 0x0`	`rfwd` `WO 0x0`
`usr` `0x7C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_usr_31to5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_usr_31to5` `RO 0x0`											`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`rsvd_busy` `RO 0x0`
`tfl` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_tfl_31toaddr_width` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_tfl_31toaddr_width` `RO 0x0`								`tfl` `RO 0x0`
`rfl` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_rfl_31toaddr_width` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_rfl_31toaddr_width` `RO 0x0`								`rfl` `RO 0x0`
`srr` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srr_31to3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srr_31to3` `RO 0x0`													`xfr` `WO 0x0`	`rfr` `WO 0x0`	`ur` `WO 0x0`
`srts` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srts_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srts_31to1` `RO 0x0`															`srts` `RW 0x0`
`sbcr` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_sbcr_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_sbcr_31to1` `RO 0x0`															`sbcr` `RW 0x0`
`sdmam` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_sdmam_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_sdmam_31to1` `RO 0x0`															`sdmam` `RW 0x0`
`sfe` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_sfe_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_sfe_31to1` `RO 0x0`															`sfe` `RW 0x0`
`srt` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srt_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srt_31to2` `RO 0x0`														`srt` `RW 0x0`
`stet` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_stet_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_stet_31to2` `RO 0x0`														`stet` `RW 0x0`
`htx` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_htx_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_htx_31to1` `RO 0x0`															`htx` `RW 0x0`
`dmasa` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_dmasa_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_dmasa_31to1` `RO 0x0`															`dmasa` `WO 0x0`
`cpr` `0xF4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_cpr_31to24` `RO 0x0`								`fifo_mode` `RO 0x8`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_cpr_15to14` `RO 0x0`		`dma_extra` `RO 0x1`	`uart_add_encoded_param` `RO 0x1`	`shadow` `RO 0x1`	`fifo_stat` `RO 0x1`	`fifo_access` `RO 0x1`	`additional_feat` `RO 0x1`	`sir_lp_mode` `RO 0x0`	`sir_mode` `RO 0x0`	`thre_mode` `RO 0x1`	`afce_mode` `RO 0x1`	`rsvd_cpr_3to2` `RO 0x0`		`apbdatawidth` `RO 0x2`
`ucv` `0xF8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`uart_component_version` `RO 0x3331342A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`uart_component_version` `RO 0x3331342A`
`ctr` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`peripheral_id` `RO 0x44570110`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`peripheral_id` `RO 0x44570110`
`i_uart_1_uart`
`rbr_thr_dll` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_rbr_thr_dll_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_rbr_thr_dll_31to8` `RO 0x0`								`value` `RW 0x0`
`ier_dlh` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_ier_dlh_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_ier_dlh_31to8` `RO 0x0`								`ptime_dlh7` `RW 0x0`	`dlh6` `RW 0x0`	`dlh5` `RW 0x0`	`dlh4` `RW 0x0`	`edssi_dhl3` `RW 0x0`	`elsi_dhl2` `RW 0x0`	`etbei_dlhl` `RW 0x0`	`erbfi_dlh0` `RW 0x0`
`iir` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_iir_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_iir_31to8` `RO 0x0`								`fifoen` `RO 0x0`		`rsvd_iir_5to4` `RO 0x0`		`id` `RO 0x1`
`fcr` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`rt` `WO 0x0`		`tet` `WO 0x0`		`dmam` `WO 0x0`	`xfifor` `WO 0x0`	`rfifor` `WO 0x0`	`fifoe` `WO 0x0`
`lcr` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_lcr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_lcr_31to8` `RO 0x0`								`dlab` `RW 0x0`	`break` `RW 0x0`	`sp` `RW 0x0`	`eps` `RW 0x0`	`pen` `RW 0x0`	`stop` `RW 0x0`	`dls` `RW 0x0`
`mcr` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_mcr_31to7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_mcr_31to7` `RO 0x0`									`sire` `RO 0x0`	`afce` `RW 0x0`	`loopback` `RW 0x0`	`out2` `RW 0x0`	`out1` `RW 0x0`	`rts` `RW 0x0`	`dtr` `RW 0x0`
`lsr` `0x14`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_lsr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_lsr_31to8` `RO 0x0`								`rfe` `RO 0x0`	`temt` `RO 0x1`	`thre` `RO 0x1`	`bi` `RO 0x0`	`fe` `RO 0x0`	`pe` `RO 0x0`	`oe` `RO 0x0`	`dr` `RO 0x0`
`msr` `0x18`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_msc_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_msc_31to8` `RO 0x0`								`dcd` `RO 0x0`	`ri` `RO 0x0`	`dsr` `RO 0x0`	`cts` `RO 0x0`	`ddcd` `RO 0x0`	`teri` `RO 0x0`	`ddsr` `RO 0x0`	`dcts` `RO 0x0`
`scr` `0x1C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_scr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_scr_31to8` `RO 0x0`								`scr` `RW 0x0`
`srbr_sthr_0` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_0_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_0_31to8` `RO 0x0`								`srbr_sthr_0` `RO 0x0`
`srbr_sthr_1` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_1_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_1_31to8` `RO 0x0`								`srbr_sthr_1` `RO 0x0`
`srbr_sthr_2` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_2_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_2_31to8` `RO 0x0`								`srbr_sthr_2` `RO 0x0`
`srbr_sthr_3` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_3_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_3_31to8` `RO 0x0`								`srbr_sthr_3` `RO 0x0`
`srbr_sthr_4` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_4_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_4_31to8` `RO 0x0`								`srbr_sthr_4` `RO 0x0`
`srbr_sthr_5` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_5_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_5_31to8` `RO 0x0`								`srbr_sthr_5` `RO 0x0`
`srbr_sthr_6` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_6_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_6_31to8` `RO 0x0`								`srbr_sthr_6` `RO 0x0`
`srbr_sthr_7` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_7_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_7_31to8` `RO 0x0`								`srbr_sthr_7` `RO 0x0`
`srbr_sthr_8` `0x50`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_8_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_8_31to8` `RO 0x0`								`srbr_sthr_8` `RO 0x0`
`srbr_sthr_9` `0x54`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_9_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_9_31to8` `RO 0x0`								`srbr_sthr_9` `RO 0x0`
`srbr_sthr_10` `0x58`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_10_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_10_31to8` `RO 0x0`								`srbr_sthr_10` `RO 0x0`
`srbr_sthr_11` `0x5C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_11_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_11_31to8` `RO 0x0`								`srbr_sthr_11` `RO 0x0`
`srbr_sthr_12` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_12_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_12_31to8` `RO 0x0`								`srbr_sthr_12` `RO 0x0`
`srbr_sthr_13` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_13_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_13_31to8` `RO 0x0`								`srbr_sthr_13` `RO 0x0`
`srbr_sthr_14` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_14_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_14_31to8` `RO 0x0`								`srbr_sthr_14` `RO 0x0`
`srbr_sthr_15` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srbr_sthr_15_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srbr_sthr_15_31to8` `RO 0x0`								`srbr_sthr_15` `RO 0x0`
`far` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_far_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_far_31to1` `RO 0x0`															`srbr_sthr` `RW 0x0`
`tfr` `0x74`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_tfr_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_tfr_31to8` `RO 0x0`								`tfr` `RO 0x0`
`rfw` `0x78`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_rfw_31to10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_rfw_31to10` `RO 0x0`						`rffe` `WO 0x0`	`rfpe` `WO 0x0`	`rfwd` `WO 0x0`
`usr` `0x7C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_usr_31to5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_usr_31to5` `RO 0x0`											`rff` `RO 0x0`	`rfne` `RO 0x0`	`tfe` `RO 0x1`	`tfnf` `RO 0x1`	`rsvd_busy` `RO 0x0`
`tfl` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_tfl_31toaddr_width` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_tfl_31toaddr_width` `RO 0x0`								`tfl` `RO 0x0`
`rfl` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_rfl_31toaddr_width` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_rfl_31toaddr_width` `RO 0x0`								`rfl` `RO 0x0`
`srr` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srr_31to3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srr_31to3` `RO 0x0`													`xfr` `WO 0x0`	`rfr` `WO 0x0`	`ur` `WO 0x0`
`srts` `0x8C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srts_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srts_31to1` `RO 0x0`															`srts` `RW 0x0`
`sbcr` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_sbcr_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_sbcr_31to1` `RO 0x0`															`sbcr` `RW 0x0`
`sdmam` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_sdmam_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_sdmam_31to1` `RO 0x0`															`sdmam` `RW 0x0`
`sfe` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_sfe_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_sfe_31to1` `RO 0x0`															`sfe` `RW 0x0`
`srt` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_srt_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_srt_31to2` `RO 0x0`														`srt` `RW 0x0`
`stet` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_stet_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_stet_31to2` `RO 0x0`														`stet` `RW 0x0`
`htx` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_htx_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_htx_31to1` `RO 0x0`															`htx` `RW 0x0`
`dmasa` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_dmasa_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_dmasa_31to1` `RO 0x0`															`dmasa` `WO 0x0`
`cpr` `0xF4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsvd_cpr_31to24` `RO 0x0`								`fifo_mode` `RO 0x8`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsvd_cpr_15to14` `RO 0x0`		`dma_extra` `RO 0x1`	`uart_add_encoded_param` `RO 0x1`	`shadow` `RO 0x1`	`fifo_stat` `RO 0x1`	`fifo_access` `RO 0x1`	`additional_feat` `RO 0x1`	`sir_lp_mode` `RO 0x0`	`sir_mode` `RO 0x0`	`thre_mode` `RO 0x1`	`afce_mode` `RO 0x1`	`rsvd_cpr_3to2` `RO 0x0`		`apbdatawidth` `RO 0x2`
`ucv` `0xF8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`uart_component_version` `RO 0x3331342A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`uart_component_version` `RO 0x3331342A`
`ctr` `0xFC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`peripheral_id` `RO 0x44570110`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`peripheral_id` `RO 0x44570110`