rfw

         Receive FIFO Write
Module Instance Base Address Register Address
i_uart_0_uart 0xFFC02000 0xFFC02078
i_uart_1_uart 0xFFC02100 0xFFC02178

Offset: 0x78

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_rfw_31to10

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_rfw_31to10

RO 0x0

rffe

WO 0x0

rfpe

WO 0x0

rfwd

WO 0x0

rfw Fields

Bit Name Description Access Reset
31:10 rsvd_rfw_31to10 
Reserved bits [31:10] - Read Only
 RO 0x0
9 rffe 
Receive FIFO Framing Error.
These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one).
When FIFO's are implemented and enabled, this bit is used to write framing error
detection information to the receive FIFO.
When FIFO's are not implemented or not enabled, this bit is used to write framing
error detection information to the RBR.
 WO 0x0
8 rfpe 
Receive FIFO Parity Error. 
These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one).
When FIFO's are implemented and enabled, this bit is used to write parity error
detection information to the receive FIFO.
When FIFO's are not implemented or not enabled, this bit is used to write parity
error detection information to the RBR.
 WO 0x0
7:0 rfwd 
Receive FIFO Write Data.
These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one).
When FIFO's are implemented and enabled, the data that is written to the RFWD is pushed
into the receive FIFO. Each consecutive write pushes the new data to the next write
location in the receive FIFO.
When FIFO's are not implemented or not enabled, the data that is written to the RFWD
is pushed into the RBR.
 WO 0x0