srts

         Shadow Request to Send.
      
Module Instance Base Address Register Address
i_uart_0_uart 0xFFC02000 0xFFC0208C
i_uart_1_uart 0xFFC02100 0xFFC0218C

Offset: 0x8C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_srts_31to1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_srts_31to1

RO 0x0

srts

RW 0x0

srts Fields

Bit Name Description Access Reset
31:1 rsvd_srts_31to1
Reserved bits [31:1] - Read Only
RO 0x0
0 srts
Shadow Request to Send.
This is a shadow register for the RTS bit (MCR[1]), this can be used to remove the
burden of having to performing a read modify write on the MCR.
This is used to directly control the Request to Send (rts_n) output. The Request
To Send (rts_n) output is used to inform the modem or data set that the UART is ready
to exchange data.
When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal is
set low by programming MCR[1] (RTS) to a high.
In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and FIFO's
enable (FCR[0] set to one), the rts_n output is controlled in the same way, but is
also gated with the receiver FIFO threshold trigger (rts_n is inactive high when
above the threshold) only when RTC Flow Trigger is disabled; otherwise it is gated by the
receiver FIFO almost-full trigger, where almost full refers to two available slots in
the FIFO (rts_n is inactive high when above the threshold).
Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive
high while the value of this location is internally looped back to an input.
Value Description
0 LOGIC1
1 LOGIC0
RW 0x0