nand_config Address Map

Module Instance	Base Address	End Address
`i_nand_config`	`0xFFB80000`	`0xFFB802FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`transfer_spare_reg`	`0x10`	`32`	`RW`	`0x0`	Default data transfer mode. (Ignored during Spare only mode)
`load_wait_cnt`	`0x20`	`32`	`RW`	`0x1F4`	Wait count value for Load operation
`program_wait_cnt`	`0x30`	`32`	`RW`	`0x1F40`	Wait count value for Program operation
`erase_wait_cnt`	`0x40`	`32`	`RW`	`0x1F40`	Wait count value for Erase operation
`int_mon_cyccnt`	`0x50`	`32`	`RW`	`0x1F4`	Interrupt monitor cycle count value
`rb_pin_enabled`	`0x60`	`32`	`RW`	`0x1`	Interrupt or polling mode. Ready/Busy pin is enabled from device.
`multiplane_operation`	`0x70`	`32`	`RW`	`0x0`	Multiplane transfer mode. Pipelined read, copyback, erase and program commands are transfered in multiplane mode
`multiplane_read_enable`	`0x80`	`32`	`RW`	`0x0`	Device supports multiplane read command sequence
`copyback_disable`	`0x90`	`32`	`RW`	`0x0`	Device does not support copyback command sequence
`cache_write_enable`	`0xA0`	`32`	`RW`	`0x0`	Device supports cache write command sequence
`cache_read_enable`	`0xB0`	`32`	`RW`	`0x0`	Device supports cache read command sequence
`prefetch_mode`	`0xC0`	`32`	`RW`	`0x1`	Enables read data prefetching to faster performance
`chip_enable_dont_care`	`0xD0`	`32`	`RW`	`0x0`	Device can work in the chip enable dont care mode
`ecc_enable`	`0xE0`	`32`	`RW`	`0x1`	Enable controller ECC check bit generation and correction
`global_int_enable`	`0xF0`	`32`	`RW`	`0x0`	Global Interrupt enable and Error/Timeout disable.
`twhr2_and_we_2_re`	`0x100`	`32`	`RW`	`0x1432`
`tcwaw_and_addr_2_data`	`0x110`	`32`	`RW`	`0x1432`
`re_2_we`	`0x120`	`32`	`RW`	`0x32`	Timing parameter between re high to we low (Trhw)
`acc_clks`	`0x130`	`32`	`RW`	`0x0`	Timing parameter from read enable going low to capture read data
`number_of_planes`	`0x140`	`32`	`RW`	`0x0`	Number of planes in the device
`pages_per_block`	`0x150`	`32`	`RW`	`0x0`	Number of pages in a block
`device_width`	`0x160`	`32`	`RW`	`0x3`	I/O width of attached devices
`device_main_area_size`	`0x170`	`32`	`RW`	`0x0`	Page main area size of device in bytes
`device_spare_area_size`	`0x180`	`32`	`RW`	`0x0`	Page spare area size of device in bytes
`two_row_addr_cycles`	`0x190`	`32`	`RW`	`0x0`	Attached device has only 2 ROW address cycles
`multiplane_addr_restrict`	`0x1A0`	`32`	`RW`	`0x0`	Address restriction for multiplane commands
`ecc_correction`	`0x1B0`	`32`	`RW`	`0x8`	Correction capability required and the Erase threshold value.
`read_mode`	`0x1C0`	`32`	`RW`	`0x0`	The type of read sequence that the controller will follow for pipe read commands.
`write_mode`	`0x1D0`	`32`	`RW`	`0x0`	The type of write sequence that the controller will follow for pipe write commands.
`copyback_mode`	`0x1E0`	`32`	`RW`	`0x0`	The type of copyback sequence that the controller will follow.
`rdwr_en_lo_cnt`	`0x1F0`	`32`	`RW`	`0x12`	Read/Write Enable low pulse width
`rdwr_en_hi_cnt`	`0x200`	`32`	`RW`	`0xC`	Read/Write Enable high pulse width
`max_rd_delay`	`0x210`	`32`	`RW`	`0x0`	Max round trip read data delay for data capture
`cs_setup_cnt`	`0x220`	`32`	`RW`	`0xA003`	Chip select setup/tWB time
`spare_area_skip_bytes`	`0x230`	`32`	`RW`	`0x0`	Spare area skip bytes
`spare_area_marker`	`0x240`	`32`	`RW`	`0xFFFF`	Spare area marker value
`devices_connected`	`0x250`	`32`	`RW`	`0x0`	Number of Devices connected on one bank
`die_mask`	`0x260`	`32`	`RW`	`0x0`	Indicates the die differentiator in case of NAND devices with stacked dies.
`first_block_of_next_plane`	`0x270`	`32`	`RW`	`0x1`	The starting block address of the next plane in a multi plane device.
`write_protect`	`0x280`	`32`	`RW`	`0x1`	This register is used to control the assertion/de-assertion of the WP# pin to the device.
`re_2_re`	`0x290`	`32`	`RW`	`0x32`	Timing parameter between re high to re low (Trhz) for the next bank
`por_reset_count`	`0x2A0`	`32`	`RW`	`0x13B`	The number of cycles the controller waits after POR to issue the first RESET command to the device.
`watchdog_reset_count`	`0x2B0`	`32`	`RW`	`0x5B9A`	The number of cycles the controller waits before flagging a watchdog timeout interrupt.
`device_reset`	`0x0`	`32`	`RW`	`0x0`	Device reset. Controller sends a RESET command to device. Controller resets bit after sending command to device