usb_devgrp Address Map

Module Instance Base Address End Address
i_usbotg_0_devgrp 0xFFB00800 0xFFB00DFF
i_usbotg_1_devgrp 0xFFB40800 0xFFB40DFF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
dcfg 0x0 32 RW 0x8200000 
Device Configuration Register
dctl 0x4 32 RW 0x2 
Device Control Register
dsts 0x8 32 RO 0x2 
Device Status Register
diepmsk 0x10 32 RW 0x0 
Device IN Endpoint Common Interrupt Mask Register
doepmsk 0x14 32 RW 0x0 
Device OUT Endpoint Common Interrupt Mask Register
daint 0x18 32 RO 0x0 
Device All Endpoints Interrupt Register
daintmsk 0x1C 32 RW 0x0 
Device All Endpoints Interrupt Mask Register
dvbusdis 0x28 32 RW 0x17D7 
Device VBUS Discharge Time Register
dvbuspulse 0x2C 32 RW 0x5B8 
Device VBUS Pulsing Time Register
dthrctl 0x30 32 RW 0xC100020 
Device Threshold Control Register
diepempmsk 0x34 32 RW 0x0 
Device IN Endpoint FIFO Empty Interrupt Mask Register
diepctl0 0x100 32 RW 0x8000 
Device Control IN Endpoint 0 Control Register
diepint0 0x108 32 RW 0x80 
Device IN Endpoint 0 Interrupt Register
dieptsiz0 0x110 32 RW 0x0 
Device IN Endpoint 0 Transfer Size Register
diepdma0 0x114 32 RW 0x0 
Device IN Endpoint 0 DMA Address Register
dtxfsts0 0x118 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 0
diepdmab0 0x11C 32 RO 0x0 
Device IN Endpoint 16 Buffer Address Register
diepctl1 0x120 32 RW 0x0 
Device Control IN Endpoint 1 Control Register
diepint1 0x128 32 RW 0x80 
Device IN Endpoint 1 Interrupt Register
dieptsiz1 0x130 32 RW 0x0 
Device IN Endpoint 1 Transfer Size Register
diepdma1 0x134 32 RW 0x0 
Device IN Endpoint 1 DMA Address Register
dtxfsts1 0x138 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 1
diepdmab1 0x13C 32 RO 0x0 
Device IN Endpoint 1 Buffer Address Register
diepctl2 0x140 32 RW 0x0 
Device Control IN Endpoint 2 Control Register
diepint2 0x148 32 RW 0x80 
Device IN Endpoint 2 Interrupt Register
dieptsiz2 0x150 32 RW 0x0 
Device IN Endpoint 2 Transfer Size Register
diepdma2 0x154 32 RW 0x0 
Device IN Endpoint 2 DMA Address Register
dtxfsts2 0x158 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 2
diepdmab2 0x15C 32 RO 0x0 
Device IN Endpoint 2 Buffer Address Register
diepctl3 0x160 32 RW 0x0 
Device Control IN Endpoint 3 Control Register
diepint3 0x168 32 RW 0x80 
Device IN Endpoint 3 Interrupt Register
dieptsiz3 0x170 32 RW 0x0 
Device IN Endpoint 3 Transfer Size Register
diepdma3 0x174 32 RW 0x0 
Device IN Endpoint 3 DMA Address Register
dtxfsts3 0x178 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 3
diepdmab3 0x17C 32 RO 0x0 
Device IN Endpoint 3 Buffer Address Register
diepctl4 0x180 32 RW 0x0 
Device Control IN Endpoint 4 Control Register
diepint4 0x188 32 RW 0x80 
Device IN Endpoint 4 Interrupt Register
dieptsiz4 0x190 32 RW 0x0 
Device IN Endpoint 4 Transfer Size Register
diepdma4 0x194 32 RW 0x0 
Device IN Endpoint 4 DMA Address Register
dtxfsts4 0x198 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 4
diepdmab4 0x19C 32 RO 0x0 
Device IN Endpoint 4 Buffer Address Register
diepctl5 0x1A0 32 RW 0x0 
Device Control IN Endpoint 5 Control Register
diepint5 0x1A8 32 RW 0x80 
Device IN Endpoint 5 Interrupt Register
dieptsiz5 0x1B0 32 RW 0x0 
Device IN Endpoint 5 Transfer Size Register
diepdma5 0x1B4 32 RW 0x0 
Device IN Endpoint 5 DMA Address Register
dtxfsts5 0x1B8 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 5
diepdmab5 0x1BC 32 RO 0x0 
Device IN Endpoint 5 Buffer Address Register
diepctl6 0x1C0 32 RW 0x0 
Device Control IN Endpoint 6 Control Register
diepint6 0x1C8 32 RW 0x80 
Device IN Endpoint 6 Interrupt Register
dieptsiz6 0x1D0 32 RW 0x0 
Device IN Endpoint 6 Transfer Size Register
diepdma6 0x1D4 32 RW 0x0 
Device IN Endpoint 6 DMA Address Register
dtxfsts6 0x1D8 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 6
diepdmab6 0x1DC 32 RO 0x0 
Device IN Endpoint 6 Buffer Address Register
diepctl7 0x1E0 32 RW 0x0 
Device Control IN Endpoint 7 Control Register
diepint7 0x1E8 32 RW 0x80 
Device IN Endpoint 7 Interrupt Register
dieptsiz7 0x1F0 32 RW 0x0 
Device IN Endpoint 7 Transfer Size Register
diepdma7 0x1F4 32 RW 0x0 
Device IN Endpoint 7 DMA Address Register
dtxfsts7 0x1F8 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 7
diepdmab7 0x1FC 32 RO 0x0 
Device IN Endpoint 7 Buffer Address Register
diepctl8 0x200 32 RW 0x0 
Device Control IN Endpoint 8 Control Register
diepint8 0x208 32 RW 0x80 
Device IN Endpoint 8 Interrupt Register
dieptsiz8 0x210 32 RW 0x0 
Device IN Endpoint 8 Transfer Size Register
diepdma8 0x214 32 RW 0x0 
Device IN Endpoint 8 DMA Address Register
dtxfsts8 0x218 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 8
diepdmab8 0x21C 32 RO 0x0 
Device IN Endpoint 8 Buffer Address Register
diepctl9 0x220 32 RW 0x0 
Device Control IN Endpoint 9 Control Register
diepint9 0x228 32 RW 0x80 
Device IN Endpoint 9 Interrupt Register
dieptsiz9 0x230 32 RW 0x0 
Device IN Endpoint 9 Transfer Size Register
diepdma9 0x234 32 RW 0x0 
Device IN Endpoint 9 DMA Address Register
dtxfsts9 0x238 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 9
diepdmab9 0x23C 32 RO 0x0 
Device IN Endpoint 9 Buffer Address Register
diepctl10 0x240 32 RW 0x0 
Device Control IN Endpoint 10 Control Register
diepint10 0x248 32 RW 0x80 
Device IN Endpoint 10 Interrupt Register
dieptsiz10 0x250 32 RW 0x0 
Device IN Endpoint 10 Transfer Size Register
diepdma10 0x254 32 RW 0x0 
Device IN Endpoint 10 DMA Address Register
dtxfsts10 0x258 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 10
diepdmab10 0x25C 32 RO 0x0 
Device IN Endpoint 10 Buffer Address Register
diepctl11 0x260 32 RW 0x0 
Device Control IN Endpoint 11 Control Register
diepint11 0x268 32 RW 0x80 
Device IN Endpoint 11 Interrupt Register
dieptsiz11 0x270 32 RW 0x0 
Device IN Endpoint 11 Transfer Size Register
diepdma11 0x274 32 RW 0x0 
Device IN Endpoint 11 DMA Address Register
dtxfsts11 0x278 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 11
diepdmab11 0x27C 32 RO 0x0 
Device IN Endpoint 11 Buffer Address Register
diepctl12 0x280 32 RW 0x0 
Device Control IN Endpoint 12 Control Register
diepint12 0x288 32 RW 0x80 
Device IN Endpoint 12 Interrupt Register
dieptsiz12 0x290 32 RW 0x0 
Device IN Endpoint 12 Transfer Size Register
diepdma12 0x294 32 RW 0x0 
Device IN Endpoint 12 DMA Address Register
dtxfsts12 0x298 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 12
diepdmab12 0x29C 32 RO 0x0 
Device IN Endpoint 12 Buffer Address Register
diepctl13 0x2A0 32 RW 0x0 
Device Control IN Endpoint 13 Control Register
diepint13 0x2A8 32 RW 0x80 
Device IN Endpoint 13 Interrupt Register
dieptsiz13 0x2B0 32 RW 0x0 
Device IN Endpoint 13 Transfer Size Register
diepdma13 0x2B4 32 RW 0x0 
Device IN Endpoint 13 DMA Address Register
dtxfsts13 0x2B8 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 13
diepdmab13 0x2BC 32 RO 0x0 
Device IN Endpoint 13 Buffer Address Register
diepctl14 0x2C0 32 RW 0x0 
Device Control IN Endpoint 14 Control Register
diepint14 0x2C8 32 RW 0x80 
Device IN Endpoint 14 Interrupt Register
dieptsiz14 0x2D0 32 RW 0x0 
Device IN Endpoint 14 Transfer Size Register
diepdma14 0x2D4 32 RW 0x0 
Device IN Endpoint 14 DMA Address Register
dtxfsts14 0x2D8 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 14
diepdmab14 0x2DC 32 RO 0x0 
Device IN Endpoint 14 Buffer Address Register
diepctl15 0x2E0 32 RW 0x0 
Device Control IN Endpoint 15 Control Register
diepint15 0x2E8 32 RW 0x80 
Device IN Endpoint 15 Interrupt Register
dieptsiz15 0x2F0 32 RW 0x0 
Device IN Endpoint 15 Transfer Size Register
diepdma15 0x2F4 32 RW 0x0 
Device IN Endpoint 15 DMA Address Register
dtxfsts15 0x2F8 32 RO 0x2000 
Device IN Endpoint Transmit FIFO Status Register 15
diepdmab15 0x2FC 32 RO 0x0 
Device IN Endpoint 15 Buffer Address Register
doepctl0 0x300 32 RW 0x8000 
Device Control OUT Endpoint 0 Control Register
doepint0 0x308 32 RW 0x0 
Device OUT Endpoint 0 Interrupt Register
doeptsiz0 0x310 32 RW 0x0 
Device OUT Endpoint 0 Transfer Size Register
doepdma0 0x314 32 RW 0x0 
Device OUT Endpoint 0 DMA Address Register
doepdmab0 0x31C 32 RO 0x0 
Device OUT Endpoint 16 Buffer Address Register
doepctl1 0x320 32 RW 0x0 
Device Control OUT Endpoint 1 Control Register
doepint1 0x328 32 RW 0x0 
Device OUT Endpoint 1 Interrupt Register
doeptsiz1 0x330 32 RW 0x0 
Device OUT Endpoint 1 Transfer Size Register
doepdma1 0x334 32 RW 0x0 
Device OUT Endpoint 1 DMA Address Register
doepdmab1 0x33C 32 RO 0x0 
Device OUT Endpoint 1 Buffer Address Register
doepctl2 0x340 32 RW 0x0 
Device Control OUT Endpoint 2 Control Register
doepint2 0x348 32 RW 0x0 
Device OUT Endpoint 2 Interrupt Register
doeptsiz2 0x350 32 RW 0x0 
Device OUT Endpoint 2 Transfer Size Register
doepdma2 0x354 32 RW 0x0 
Device OUT Endpoint 2 DMA Address Register
doepdmab2 0x35C 32 RO 0x0 
Device OUT Endpoint 2 Buffer Address Register
doepctl3 0x360 32 RW 0x0 
Device Control OUT Endpoint 3 Control Register
doepint3 0x368 32 RW 0x0 
Device OUT Endpoint 3 Interrupt Register
doeptsiz3 0x370 32 RW 0x0 
Device OUT Endpoint 3 Transfer Size Register
doepdma3 0x374 32 RW 0x0 
Device OUT Endpoint 3 DMA Address Register
doepdmab3 0x37C 32 RO 0x0 
Device OUT Endpoint 3 Buffer Address Register
doepctl4 0x380 32 RW 0x0 
Device Control OUT Endpoint 4 Control Register
doepint4 0x388 32 RW 0x0 
Device OUT Endpoint 4 Interrupt Register
doeptsiz4 0x390 32 RW 0x0 
Device OUT Endpoint 4 Transfer Size Register
doepdma4 0x394 32 RW 0x0 
Device OUT Endpoint 4 DMA Address Register
doepdmab4 0x39C 32 RO 0x0 
Device OUT Endpoint 4 Buffer Address Register
doepctl5 0x3A0 32 RW 0x0 
Device Control OUT Endpoint 5 Control Register
doepint5 0x3A8 32 RW 0x0 
Device OUT Endpoint 5 Interrupt Register
doeptsiz5 0x3B0 32 RW 0x0 
Device OUT Endpoint 5 Transfer Size Register
doepdma5 0x3B4 32 RW 0x0 
Device OUT Endpoint 5 DMA Address Register
doepdmab5 0x3BC 32 RO 0x0 
Device OUT Endpoint 5 Buffer Address Register
doepctl6 0x3C0 32 RW 0x0 
Device Control OUT Endpoint 6 Control Register
doepint6 0x3C8 32 RW 0x0 
Device OUT Endpoint 6 Interrupt Register
doeptsiz6 0x3D0 32 RW 0x0 
Device OUT Endpoint 6 Transfer Size Register
doepdma6 0x3D4 32 RW 0x0 
Device OUT Endpoint 6 DMA Address Register
doepdmab6 0x3DC 32 RO 0x0 
Device OUT Endpoint 6 Buffer Address Register
doepctl7 0x3E0 32 RW 0x0 
Device Control OUT Endpoint 7 Control Register
doepint7 0x3E8 32 RW 0x0 
Device OUT Endpoint 7 Interrupt Register
doeptsiz7 0x3F0 32 RW 0x0 
Device OUT Endpoint 7 Transfer Size Register
doepdma7 0x3F4 32 RW 0x0 
Device OUT Endpoint 7 DMA Address Register
doepdmab7 0x3FC 32 RO 0x0 
Device OUT Endpoint 7 Buffer Address Register
doepctl8 0x400 32 RW 0x0 
Device Control OUT Endpoint 8 Control Register
doepint8 0x408 32 RW 0x0 
Device OUT Endpoint 8 Interrupt Register
doeptsiz8 0x410 32 RW 0x0 
Device OUT Endpoint 8 Transfer Size Register
doepdma8 0x414 32 RW 0x0 
Device OUT Endpoint 8 DMA Address Register
doepdmab8 0x41C 32 RO 0x0 
Device OUT Endpoint 8 Buffer Address Register
doepctl9 0x420 32 RW 0x0 
Device Control OUT Endpoint 9 Control Register
doepint9 0x428 32 RW 0x0 
Device OUT Endpoint 9 Interrupt Register
doeptsiz9 0x430 32 RW 0x0 
Device OUT Endpoint 9 Transfer Size Register
doepdma9 0x434 32 RW 0x0 
Device OUT Endpoint 9 DMA Address Register
doepdmab9 0x43C 32 RO 0x0 
Device OUT Endpoint 9 Buffer Address Register
doepctl10 0x440 32 RW 0x0 
Device Control OUT Endpoint 10 Control Register
doepint10 0x448 32 RW 0x0 
Device OUT Endpoint 10 Interrupt Register
doeptsiz10 0x450 32 RW 0x0 
Device OUT Endpoint 10 Transfer Size Register
doepdma10 0x454 32 RW 0x0 
Device OUT Endpoint 10 DMA Address Register
doepdmab10 0x45C 32 RO 0x0 
Device OUT Endpoint 10 Buffer Address Register
doepctl11 0x460 32 RW 0x0 
Device Control OUT Endpoint 11 Control Register
doepint11 0x468 32 RW 0x0 
Device OUT Endpoint 11 Interrupt Register
doeptsiz11 0x470 32 RW 0x0 
Device OUT Endpoint 11 Transfer Size Register
doepdma11 0x474 32 RW 0x0 
Device OUT Endpoint 11 DMA Address Register
doepdmab11 0x47C 32 RO 0x0 
Device OUT Endpoint 11 Buffer Address Register
doepctl12 0x480 32 RW 0x0 
Device Control OUT Endpoint 12 Control Register
doepint12 0x488 32 RW 0x0 
Device OUT Endpoint 12 Interrupt Register
doeptsiz12 0x490 32 RW 0x0 
Device OUT Endpoint 12 Transfer Size Register
doepdma12 0x494 32 RW 0x0 
Device OUT Endpoint 12 DMA Address Register
doepdmab12 0x49C 32 RO 0x0 
Device OUT Endpoint 12 Buffer Address Register
doepctl13 0x4A0 32 RW 0x0 
Device Control OUT Endpoint 13 Control Register
doepint13 0x4A8 32 RW 0x0 
Device OUT Endpoint 13 Interrupt Register
doeptsiz13 0x4B0 32 RW 0x0 
Device OUT Endpoint 13 Transfer Size Register
doepdma13 0x4B4 32 RW 0x0 
Device OUT Endpoint 13 DMA Address Register
doepdmab13 0x4BC 32 RO 0x0 
Device OUT Endpoint 13 Buffer Address Register
doepctl14 0x4C0 32 RW 0x0 
Device Control OUT Endpoint 14 Control Register
doepint14 0x4C8 32 RW 0x0 
Device OUT Endpoint 14 Interrupt Register
doeptsiz14 0x4D0 32 RW 0x0 
Device OUT Endpoint 14 Transfer Size Register
doepdma14 0x4D4 32 RW 0x0 
Device OUT Endpoint 14 DMA Address Register
doepdmab14 0x4DC 32 RO 0x0 
Device OUT Endpoint 14 Buffer Address Register
doepctl15 0x4E0 32 RW 0x0 
Device Control OUT Endpoint 15 Control Register
doepint15 0x4E8 32 RW 0x0 
Device OUT Endpoint 15 Interrupt Register
doeptsiz15 0x4F0 32 RW 0x0 
Device OUT Endpoint 15 Transfer Size Register
doepdma15 0x4F4 32 RW 0x0 
Device OUT Endpoint 15 DMA Address Register
doepdmab15 0x4FC 32 RO 0x0 
Device OUT Endpoint 15 Buffer Address Register