dcfg

         Device Configuration Register
      
Module Instance Base Address Register Address
i_usbotg_0_devgrp 0xFFB00800 0xFFB00800
i_usbotg_1_devgrp 0xFFB40800 0xFFB40800

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

resvalid

RW 0x2

perschintvl

RW 0x0

descdma

RW 0x0

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

erraticintmsk

RW 0x0

xcvrdly

RW 0x0

endevoutnak

RW 0x0

perfrint

RW 0x0

devaddr

RW 0x0

ena32khzsusp

RW 0x0

nzstsouthshk

RW 0x0

devspd

RW 0x0

dcfg Fields

Bit Name Description Access Reset
31:26 resvalid
Resume Validation Period (ResValid)
This field is effective only when DCFG.Ena32KHzSusp is set.
It will control the resume period when the core resumes from
suspend. The core counts for “ResValid” number of clock cycles 
to detect a valid resume when this is set
RW 0x2
25:24 perschintvl
Periodic Scheduling Interval (PerSchIntvl)
PerSchIntvl must be programmed only For Scatter/Gather DMA
mode.
Description: This field specifies the amount of time the Internal
DMA engine must allocate For fetching periodic IN endpoint data.
Based on the number of periodic endpoints, this value must be
specified as 25,50 or 75% of (micro)frame.
 When any periodic endpoints are active, the internal DMA
engine allocates the specified amount of time in fetching
periodic IN endpoint data .
 When no periodic endpoints are active, Then the internal
DMA engine services non-periodic endpoints, ignoring this
field.
After the specified time within a (micro)frame, the DMA switches
to fetching For non-periodic endpoints.
 2'b00: 25% of (micro)frame.
 2'b01: 50% of (micro)frame.
 2'b10: 75% of (micro)frame.
 2'b11: Reserved.
Reset: 2'b00
Value Description
0x0 MF25
0x1 MF50
0x2 MF75
0x3 RESERVED
RW 0x0
23 descdma
Enable Scatter/gather DMA in device mode (DescDMA).
When the Scatter/Gather DMA option selected during
configuration of the RTL, the application can Set this bit during
initialization to enable the Scatter/Gather DMA operation.
NOTE: This bit must be modified only once after a reset.
The following combinations are available For programming:
 GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode
 GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid
 GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA
mode
 GAHBCFG.DMAEn=1,DCFG.DescDMA=1 =>
Scatter/Gather DMA mode
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
15 erraticintmsk
Erratic Error Interrupt Mask
1'b1: Mask early suspend interrupt on erratic error
1'b0: Early suspend interrupt is generated on erratic error
RW 0x0
14 xcvrdly
1'b1: Enable delay between xcvr_sel and txvalid during Device chirp
1'b0: No delay between xcvr_sel and txvalid during Device chirp
RW 0x0
13 endevoutnak
  Enable Device OUT NAK (EnDevOutNak)
This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed 
for Device mode Descriptor DMA 
	1'b0 : The core does not set NAK after Bulk OUT transfer complete
	1'b1  :  The core sets NAK after Bulk OUT transfer complete
It is one time
programmable after reset like any other DCFG register bits.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
12:11 perfrint
Periodic Frame Interval (PerFrInt)
Indicates the time within a (micro)frame at which the application
must be notified using the End Of Periodic Frame Interrupt. This
can be used to determine If all the isochronous traffic For that
(micro)frame is complete.
 2'b00: 80% of the (micro)frame interval
 2'b01: 85%
 2'b10: 90%
 2'b11: 95%
Value Description
0x0 EOPF80
0x1 EOPF85
0x2 EOPF90
0x3 EOPF95
RW 0x0
10:4 devaddr
Device Address (DevAddr)
The application must program this field after every SetAddress
control command.
RW 0x0
3 ena32khzsusp
Enable 32 KHz Suspend mode (Ena32KHzSusp) 
This bit can be set only if FS PHY interface is selected. Else, 
this bit needs to be set to zero. When FS PHY interface is chosen 
and this bit is set, the core expects that the PHY clock during 
Suspend is switched from 48 MHz to 32 KHz.
Value Description
0x0 DISABLED
0x1 ENABLED
RW 0x0
2 nzstsouthshk
Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)
The application can use this field to select the handshake the
core sends on receiving a nonzero-length data packet during the
OUT transaction of a control transfer's Status stage.
 1'b1: Send a STALL handshake on a nonzero-length status
OUT transaction and do not send the received OUT packet to
the application.
 1'b0: Send the received OUT packet to the application (zerolength
or nonzero-length) and send a handshake based on
the NAK and STALL bits For the endpoint in the Device
Endpoint Control register.
Value Description
0x0 SENDOUT
0x1 SENDSTALL
RW 0x0
1:0 devspd
Device Speed (DevSpd)
Indicates the speed at which the application requires the core to
enumerate, or the maximum speed the application can support.
However, the actual bus speed is determined only after the chirp
sequence is completed, and is based on the speed of the USB
host to which the core is connected. See “Device Initialization”
.
 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz). If
you select 6 MHz LS mode, you must do a soft reset.
 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz)
Value Description
0x0 USBHS20
0x1 USBFS20
0x2 USBLS116
0x3 USBLS1148
RW 0x0