rf_minictrl_regs Address Map


Module Instance	Base Address	End Address
`i_nand__reg_apb__10b80000__rf_minictrl_regs__SEG_L4_MP_nand_s_0x0_0x10000`	`0x10B81000`	`0x10B81037`


Register	Offset	Width	Access	Reset Value	Description
`wp_settings`	`0x0`	`32`	`RO`	`0x00000001`	Write Protect
`rbn_settings`	`0x4`	`32`	`RO`	`0x00000000`	Ready/Busy# line status. Represents the value of the Ready/Busy# lines after two stage synchronizers due to the asynchronous nature of R/B#.
`common_settings`	`0x8`	`32`	`RO`	`0x00000000`	Configuration of the Minicontroller.
`skip_bytes_conf`	`0xC`	`32`	`RW`	`0x00000000`	Skip bytes settings.
`skip_bytes_offset`	`0x10`	`32`	`RO`	`0x00000000`	Skip bytes offset settings.
`toggle_timings_0`	`0x14`	`32`	`RO`	`0x3F3F3F3F`	Toggle Mode/NV-DDR2/NV-DDR3 timings configuration.
`toggle_timings_1`	`0x18`	`32`	`RO`	`0x7F3F3F3F`	Toggle Mode/NV-DDR2/NV-DDR3 timings configuration. Timing tWPST is also valid in NV-DDR mode.
`async_toggle_timings`	`0x1C`	`32`	`RO`	`0x18181818`	Toggle Mode/NV-DDR2/NV-DDR3 and SDR timings configuration.
`sync_timings`	`0x20`	`32`	`RO`	`0x003F3F3F`	Source Synchronous/NV-DDR timings configuration.
`timings0`	`0x24`	`32`	`RW`	`0xFFFFFFFF`	Global timings configuration - register 0.
`timings1`	`0x28`	`32`	`RW`	`0xFFFFFFFF`	Global timings configuration - register 1.
`timings2`	`0x2C`	`32`	`RO`	`0x03FF3F3F`	Global timings configuration - register 2.
`dll_phy_update_cnt`	`0x30`	`32`	`RW`	`0x00000000`	Configuration of the resynchronization of slave DLL of PHY.
`dll_phy_ctrl`	`0x34`	`32`	`RO`	`0x01030707`	Configuration of the resynchronization of slave DLL of PHY.