timings1 

         Global timings configuration - register 1.
Module Instance Base Address Register Address
i_nand__reg_apb__10b80000__rf_minictrl_regs__SEG_L4_MP_nand_s_0x0_0x10000 0x10B81000 0x10B81028

Size: 32

Offset: 0x28

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

tRHZ

RW 0xFF

tWB

RW 0xFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

tCWAW

RW 0xFF

tVDLY

RW 0xFF

timings1 Fields

Bit Name Description Access Reset
31:24 tRHZ 
              Timing parameter between re high to re low for the next bank. The timing value follows tRHZ.
              The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk)
              that would be required to satisfy the time.
              This timing is not used in the NV-DDR mode.
RW 0xFF
23:16 tWB 
)
              signal
RW 0xFF
15:8 tCWAW 
Signifies the number of Minicontroller clock cycles (nf_clk) that should be introduced between the command cycle of a random data input command to the address cycle of the random data input command. The timing value follows tCWAW.
 RW 0xFF
7:0 tVDLY 
Signifies the number of Minicontroller clock cycles (nf_clk) that should be introduced after a volume select command before de-asserting the CE or before sending a command to the new volume. The timing value follows tVDLY.
 RW 0xFF