sync_timings 

         Source Synchronous/NV-DDR timings configuration.
Module Instance Base Address Register Address
i_nand__reg_apb__10b80000__rf_minictrl_regs__SEG_L4_MP_nand_s_0x0_0x10000 0x10B81000 0x10B81020

Size: 32

Offset: 0x20

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_3

RO 0x0

tCKWR

RW 0x3F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

tWRCK

RW 0x3F

Reserved_1

RO 0x0

tCAD

RW 0x3F

sync_timings Fields

Bit Name Description Access Reset
31:22 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
21:16 tCKWR 
Timing parameter between end of the data output cycle and de-asserting the rebar signal . The timing value follows tCKWR. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time.
 RW 0x3F
15:14 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
13:8 tWRCK 
Timing parameter between driving the rebar signal low and start data output cycle. The timing value follows tWRCK. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time.
 RW 0x3F
7:6 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
5:0 tCAD 
Timing parameter between command, address and data cycles in synchronous mode. The timing value follows tCAD. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time.
 RW 0x3F