rf_minictrl_regs Summary

Base Address: 0x10B81000


Register Address Offset	Bit Fields
`i_nand__reg_apb__10b80000__rf_minictrl_regs__SEG_L4_MP_nand_s_0x0_0x10000`
`wp_settings` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`WP` `RW 0x1`
`rbn_settings` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`Rbn` `RO 0x0`
`common_settings` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`								`Reseerved` `RW 0x0`				`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`							`device_16bit` `RW 0x0`	`Reserved_1` `RO 0x0`						`opr_mode` `RW 0x0`
`skip_bytes_conf` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`marker` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`								`skip_bytes` `RW 0x0`
`skip_bytes_offset` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_1` `RO 0x0`								`skip_bytes_offset` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`skip_bytes_offset` `RW 0x0`
`toggle_timings_0` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`		`tCR` `RW 0x3F`						`Reserved_3` `RO 0x0`		`tPRE` `RW 0x3F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`		`tCDQSS` `RW 0x3F`						`Reserved_1` `RO 0x0`		`tPSTH` `RW 0x3F`
`toggle_timings_1` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`	`tCDQSH` `RW 0x7F`							`Reserved_3` `RO 0x0`		`tCRES` `RW 0x3F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`		`tRPST` `RW 0x3F`						`Reserved_1` `RO 0x0`		`tWPST` `RW 0x3F`
`async_toggle_timings` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`			`tRH` `RW 0x18`					`Reserved_3` `RO 0x0`			`tRP` `RW 0x18`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`			`tWH` `RW 0x18`					`Reserved_1` `RO 0x0`			`tWP` `RW 0x18`
`sync_timings` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`										`tCKWR` `RW 0x3F`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`		`tWRCK` `RW 0x3F`						`Reserved_1` `RO 0x0`		`tCAD` `RW 0x3F`
`timings0` `0x36` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`tADL` `RW 0xFF`								`tCCS` `RW 0xFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tWHR` `RW 0xFF`								`tRHW` `RW 0xFF`
`timings1` `0x40` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`tRHZ` `RW 0xFF`								`tWB` `RW 0xFF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`tCWAW` `RW 0xFF`								`tVDLY` `RW 0xFF`
`timings2` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`						`tFEAT` `RW 0x3FF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`		`CS_hold_time` `RW 0x3F`						`Reserved_1` `RO 0x0`		`CS_setup_time` `RW 0x3F`
`dll_phy_update_cnt` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`resync_cnt` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`resync_cnt` `RW 0x0`
`dll_phy_ctrl` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_7` `RO 0x0`					`dll_lock_done` `RO 0x0`	`dfi_ctrlupd_req` `RW 0x0`	`dll_rst_n` `RW 0x1`	`Reserved_4` `RO 0x0`						`extended_wr_mode` `RW 0x1`	`extended_rd_mode` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_2` `RO 0x0`				`resync_high_wait_cnt` `RW 0x7`				`resync_idle_cnt` `RW 0x7`