WD0_csr Address Map


Module Instance	Base Address	End Address
`i_watchdog_0__watchdog_csr__10d00200__wdt_address_block__SEG_L4_SYS1_wd0_0x0_0x100`	`0x10D00200`	`0x10D002FF`


Register	Offset	Width	Access	Reset Value	Description
`WDT_CR`	`0x0`	`32`	`RW`	`0x00000010`	Control Register
`WDT_TORR`	`0x4`	`32`	`RW`	`0x000000FF`	Timeout Range Register
`WDT_CCVR`	`0x8`	`32`	`RO`	`0x7FFFFFFF`	Current Counter Value Register
`WDT_CRR`	`0xC`	`32`	`WO`	`0x00000000`	Counter Restart Register
`WDT_STAT`	`0x10`	`32`	`RO`	`0x00000000`	Interrupt Status Register
`WDT_EOI`	`0x14`	`32`	`RO`	`0x00000000`	Interrupt Clear Register
`WDT_COMP_PARAM_1`	`0xF4`	`32`	`RO`	`0x10FF1244`	Component Parameters Register 1
`WDT_COMP_VERSION`	`0xF8`	`32`	`RO`	`0x3130382A`	Component Version Register
`WDT_COMP_TYPE`	`0xFC`	`32`	`RO`	`0x44570120`	Component Type Register