WDT_CRR

         Counter Restart Register.


Module Instance	Base Address	Register Address
`i_watchdog_0__watchdog_csr__10d00200__wdt_address_block__SEG_L4_SYS1_wd0_0x0_0x100`	`0x10D00200`	`0x10D0020C`

Size: 32

Offset: 0xC

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_1` `WO 0x0`								`wdt_crr` `WO 0x0`

WDT_CRR Fields

Bit Name Description Access Reset

31:8

Reserved_1

Reserved bitfield added by Magillem

WO

0x0

7:0

wdt_crr

This register is used to restart the WDT counter. As a safety feature to
prevent accidental restarts, the value 0x76 must be written. A restart also
clears the WDT interrupt. Reading this register returns zero.

Value	Description
0x76	Watchdog timer restart command

WO

0x0