WDT_CR

         Control Register


Module Instance	Base Address	Register Address
`i_watchdog_0__watchdog_csr__10d00200__wdt_address_block__SEG_L4_SYS1_wd0_0x0_0x100`	`0x10D00200`	`0x10D00200`

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_3` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_3` `RO 0x0`											`RPL` `RW 0x4`			`RMOD` `RW 0x0`	`WDT_EN` `RW 0x0`

WDT_CR Fields

Bit Name Description Access Reset

31:5

Reserved_3

Reserved bitfield added by Magillem

RO

0x0

4:2

RPL

Reset pulse length. Writes have no effect when the configuration parameter
WDT_HC_RPL is 1, making the register bits read-only. This is used to select
the number of pclk cycles for which the system reset stays asserted. The
range of values available is 2 to 256 pclk cycles.
000 - 2 pclk cycles
001 - 4 pclk cycles
010 - 8 pclk cycles
011 - 16 pclk cycles
100 - 32 pclk cycles
101 - 64 pclk cycles
110 - 128 pclk cycles
111 - 256 pclk cycles

Value	Description
0x0	2 pclk cycles
0x1	4 pclk cycles
0x2	8 pclk cycles
0x3	16 pclk cycles
0x4	32 pclk cycles
0x5	64 pclk cycles
0x6	128 pclk cycles
0x7	256 pclk cycles

RW

0x4

RMOD

Response mode. Writes have no effect when the parameter
WDT_HC_RMOD = 1, thus this register becomes read-only.
Selects the output response generated to a timeout.
0 = Generate a system reset.
1 = First generate an interrupt and if it is not cleared by the time
    a second timeout occurs then generate a system reset.

Value	Description
0x0	Generate a system reset
0x1	First generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset

RW

0x0

WDT_EN

When the configuration parameter WDT_ALWAYS_EN = 0, this bit can be set
otherwise, it is read-only. This bit is used to enable and disable the DW_apb_wdt. 
When disabled, the counter does not decrement. Thus, no interrupts or system resets
are generated.
The DW_apb_wdt is used to prevent system lock-up. To prevent a software bug from
disabling the DW_apb_wdt, once this bit has been enabled, it can be cleared only by
a system reset.
0 = WDT disabled.
1 = WDT enabled.

Value	Description
0x0	Watchdog timer disabled
0x1	Watchdog timer enabled

RW

0x0