UART0 Summary

Base Address: 0x10C02000


Register Address Offset	Bit Fields
`i_uart_0__uart_csr__10c02000__uart_address_block__SEG_L4_SP_uart0_0x0_0x100`
`RBR` `0x0` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_RBR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_RBR_31to8` `RO 0x0`								`rbr` `RO 0x0`
`IER` `0x4` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_IER_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_IER_31to8` `RO 0x0`								`PTIME` `RW 0x0`	`RSVD_IER_6to4` `RO 0x0`			`EDSSI` `RW 0x0`	`ELSI` `RW 0x0`	`ETBEI` `RW 0x0`	`ERBFI` `RW 0x0`
`IIR` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_IIR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_IIR_31to8` `RO 0x0`								`FIFOSE` `RO 0x0`		`RSVD_IIR_5to4` `RO 0x0`		`IID` `RO 0x1`
`LCR` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_LCR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_LCR_31to8` `RO 0x0`								`DLAB` `RW 0x0`	`Break` `RW 0x0`	`SP` `RW 0x0`	`EPS` `RW 0x0`	`PEN` `RW 0x0`	`STOP` `RW 0x0`	`DLS` `RW 0x0`
`MCR` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_MCR_31to7` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_MCR_31to7` `RO 0x0`									`SIRE` `RO 0x0`	`AFCE` `RW 0x0`	`LoopBack` `RW 0x0`	`OUT2` `RW 0x0`	`OUT1` `RW 0x0`	`RTS` `RW 0x0`	`DTR` `RW 0x0`
`LSR` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_LSR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_LSR_31to8` `RO 0x0`								`RFE` `RO 0x0`	`TEMT` `RO 0x1`	`THRE` `RO 0x1`	`BI` `RO 0x0`	`FE` `RO 0x0`	`PE` `RO 0x0`	`OE` `RO 0x0`	`DR` `RO 0x0`
`MSR` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_MSR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_MSR_31to8` `RO 0x0`								`DCD` `RO 0x0`	`RI` `RO 0x0`	`DSR` `RO 0x0`	`CTS` `RO 0x0`	`DDCD` `RO 0x0`	`TERI` `RO 0x0`	`DDSR` `RO 0x0`	`DCTS` `RO 0x0`
`SCR` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SCR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SCR_31to8` `RO 0x0`								`scr` `RW 0x0`
`SRBR0` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR0_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR0_31to8` `RO 0x0`								`srbr0` `RO 0x0`
`SRBR1` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR1_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR1_31to8` `RO 0x0`								`srbr1` `RO 0x0`
`SRBR2` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR2_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR2_31to8` `RO 0x0`								`srbr2` `RO 0x0`
`SRBR3` `0x60` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR3_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR3_31to8` `RO 0x0`								`srbr3` `RO 0x0`
`SRBR4` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR4_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR4_31to8` `RO 0x0`								`srbr4` `RO 0x0`
`SRBR5` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR5_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR5_31to8` `RO 0x0`								`srbr5` `RO 0x0`
`SRBR6` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR6_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR6_31to8` `RO 0x0`								`srbr6` `RO 0x0`
`SRBR7` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR7_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR7_31to8` `RO 0x0`								`srbr7` `RO 0x0`
`SRBR8` `0x80` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR8_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR8_31to8` `RO 0x0`								`srbr8` `RO 0x0`
`SRBR9` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR9_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR9_31to8` `RO 0x0`								`srbr9` `RO 0x0`
`SRBR10` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR10_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR10_31to8` `RO 0x0`								`srbr10` `RO 0x0`
`SRBR11` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR11_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR11_31to8` `RO 0x0`								`srbr11` `RO 0x0`
`SRBR12` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR12_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR12_31to8` `RO 0x0`								`srbr12` `RO 0x0`
`SRBR13` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR13_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR13_31to8` `RO 0x0`								`srbr13` `RO 0x0`
`SRBR14` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR14_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR14_31to8` `RO 0x0`								`srbr14` `RO 0x0`
`SRBR15` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRBR15_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRBR15_31to8` `RO 0x0`								`srbr15` `RO 0x0`
`FAR` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_FAR_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_FAR_31to1` `RO 0x0`															`far` `RW 0x0`
`TFR` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_TFR_31to8` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_TFR_31to8` `RO 0x0`								`tfr` `RO 0x0`
`RFW` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_RFW_31to10` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_RFW_31to10` `RO 0x0`						`RFFE` `WO 0x0`	`RFPE` `WO 0x0`	`RFWD` `WO 0x0`
`USR` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_USR_31to5` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_USR_31to5` `RO 0x0`											`RFF` `RO 0x0`	`RFNE` `RO 0x0`	`TFE` `RO 0x1`	`TFNF` `RO 0x1`	`RSVD_BUSY` `RO 0x0`
`TFL` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_TFL_31toADDR_WIDTH` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_TFL_31toADDR_WIDTH` `RO 0x0`								`tfl` `RO 0x0`
`RFL` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_RFL_31toADDR_WIDTH` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_RFL_31toADDR_WIDTH` `RO 0x0`								`rfl` `RO 0x0`
`SRR` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRR_31to3` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRR_31to3` `RO 0x0`													`XFR` `WO 0x0`	`RFR` `WO 0x0`	`UR` `WO 0x0`
`SRTS` `0x140` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRTS_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRTS_31to1` `RO 0x0`															`srts` `RW 0x0`
`SBCR` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SBCR_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SBCR_31to1` `RO 0x0`															`sbcb` `RW 0x0`
`SDMAM` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SDMAM_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SDMAM_31to1` `RO 0x0`															`sdmam` `RW 0x0`
`SFE` `0x152` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SFE_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SFE_31to1` `RO 0x0`															`sfe` `RW 0x0`
`SRT` `0x156` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_SRT_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_SRT_31to2` `RO 0x0`														`srt` `RW 0x0`
`STET` `0x160` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_STET_31to2` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_STET_31to2` `RO 0x0`														`stet` `RW 0x0`
`HTX` `0x164` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_HTX_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_HTX_31to1` `RO 0x0`															`htx` `RW 0x0`
`DMASA` `0x168` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_DMASA_31to1` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_DMASA_31to1` `RO 0x0`															`dmasa` `WO 0x0`
`CPR` `0x244` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`RSVD_CPR_31to24` `RO 0x0`								`FIFO_MODE` `RO 0x8`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`RSVD_CPR_15to14` `RO 0x0`		`DMA_EXTRA` `RO 0x1`	`UART_ADD_ENCODED_PARAMS` `RO 0x1`	`SHADOW` `RO 0x1`	`FIFO_STAT` `RO 0x1`	`FIFO_ACCESS` `RO 0x1`	`ADDITIONAL_FEAT` `RO 0x1`	`SIR_LP_MODE` `RO 0x0`	`SIR_MODE` `RO 0x0`	`THRE_MODE` `RO 0x1`	`AFCE_MODE` `RO 0x1`	`RSVD_CPR_3to2` `RO 0x0`		`APB_DATA_WIDTH` `RO 0x2`
`UCV` `0x248` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`UART_Component_Version` `RO 0x3331352A`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`UART_Component_Version` `RO 0x3331352A`
`CTR` `0x252` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Peripheral_ID` `RO 0x44570110`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Peripheral_ID` `RO 0x44570110`