DMASA

         DMA Software Acknowledge


Module Instance	Base Address	Register Address
`i_uart_0__uart_csr__10c02000__uart_address_block__SEG_L4_SP_uart0_0x0_0x100`	`0x10C02000`	`0x10C020A8`

Size: 32

Offset: 0xA8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMASA_31to1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMASA_31to1` `RO 0x0`															`dmasa` `WO 0x0`

DMASA Fields

Bit Name Description Access Reset

31:1

RSVD_DMASA_31to1

Reserved bits [31:1] - Read Only

RO

0x0

dmasa

DMA Software Acknowledge.
Writes will have no effect when DMA_EXTRA == No.  This register is use to perform
DMA software acknowledge if a transfer needs to be terminated due to an error
condition. For example, if the DMA disables the channel, then the DW_apb_uart should
clear its request. This will cause the TX request, TX single, RX request and RX
single signals to de-assert.
Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

Value	Description
0x1	DMA software acknowledge

WO

0x0