TFL

         Transmit FIFO Level.
This register is valid only when the DW_apb_uart is configured to have additional FIFO status registers
implemented (FIFO_STAT = YES). If status registers are not implemented, this register does not exist and
reading from this register address returns 0.


Module Instance	Base Address	Register Address
`i_uart_0__uart_csr__10c02000__uart_address_block__SEG_L4_SP_uart0_0x0_0x100`	`0x10C02000`	`0x10C02080`

Size: 32

Offset: 0x80

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_TFL_31toADDR_WIDTH` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_TFL_31toADDR_WIDTH` `RO 0x0`								`tfl` `RO 0x0`

TFL Fields


Bit	Name	Description	Access	Reset
31:8	`RSVD_TFL_31toADDR_WIDTH`	Reserved bits: 31 downto addr bus width + 1 - Read Only	`RO`	`0x0`
7:0	`tfl`	Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO.	`RO`	`0x0`