OCRAM_firewall Address Map

OCRAM Security Control Registers (SCR)


Module Instance	Base Address	End Address
`i_soc_ocram_firewall__fw_ocram__108cc400__ocram_firewall__SEG_L4_ocram_0x0_0x800`	`0x108CC400`	`0x108CC5FF`


Register	Offset	Width	Access	Reset Value	Description
`enable`	`0x0`	`32`	`RO`	`0x00000001`	Enable
`enable_set`	`0x4`	`32`	`WO`	`0x00000000`	Sets Master Region Enable field when written with 1
`enable_clear`	`0x8`	`32`	`WO`	`0x00000000`	Clears Master Region Enable field when written with 1
`region0_base_adresss`	`0x10`	`32`	`RW`	`0x00000000`	Base definition for OCRAM Region 0
`region0_limit_adresss`	`0x14`	`32`	`RW`	`0x0007FFFF`	Base definition for OCRAM Region 0
`region0_access`	`0x18`	`32`	`RW`	`0x00000001`	Base definition for OCRAM Region 0
`region1_base_adresss`	`0x1C`	`32`	`RW`	`0x00000000`	Base definition for OCRAM Region 0
`region1_limit_adresss`	`0x20`	`32`	`RW`	`0x0007FFFF`	Base definition for OCRAM Region 0
`region1_access`	`0x24`	`32`	`RW`	`0x00000001`	Base definition for OCRAM Region 0
`region2_base_adresss`	`0x28`	`32`	`RW`	`0x00000000`	Base definition for OCRAM Region 0
`region2_limit_adresss`	`0x2C`	`32`	`RW`	`0x0007FFFF`	Base definition for OCRAM Region 0
`region2_access`	`0x30`	`32`	`RW`	`0x00000001`	Base definition for OCRAM Region 0
`region3_base_adresss`	`0x34`	`32`	`RW`	`0x00000000`	Base definition for OCRAM Region 0
`region3_limit_adresss`	`0x38`	`32`	`RW`	`0x0007FFFF`	Base definition for OCRAM Region 0
`region3_access`	`0x3C`	`32`	`RW`	`0x00000001`	Base definition for OCRAM Region 0