enable

         Enable


Module Instance	Base Address	Register Address
`i_soc_ocram_firewall__fw_ocram__108cc400__ocram_firewall__SEG_L4_ocram_0x0_0x800`	`0x108CC400`	`0x108CC400`

Size: 32

Offset: 0x

Access: RO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RVSD` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RVSD` `RO 0x0`												`region3` `RO 0x0`	`region2` `RO 0x0`	`region1` `RO 0x0`	`region0` `RO 0x1`

enable Fields


Bit	Name	Description	Access	Reset
31:4	`RVSD`	MSB field is all zeros.	`RO`	`0x0`
3	`region3`	OCRAM Region 3 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RO`	`0x0`
2	`region2`	OCRAM Region 2 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RO`	`0x0`
1	`region1`	OCRAM Region 1 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RO`	`0x0`
0	`region0`	OCRAM Region 0 Enable. Value of 1 means region is enabled, Value of 0 means region is disabled	`RO`	`0x1`