region0_limit_adresss

         Base definition for OCRAM Region 0


Module Instance	Base Address	Register Address
`i_soc_ocram_firewall__fw_ocram__108cc400__ocram_firewall__SEG_L4_ocram_0x0_0x800`	`0x108CC400`	`0x108CC414`

Size: 32

Offset: 0x14

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`high_fixed` `RO 0x0`				`select` `RW 0x7F`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`select` `RW 0x7F`				`low_fixed` `RO 0xFFF`

region0_limit_adresss Fields


Bit	Name	Description	Access	Reset
31:28	`high_fixed`	RSVD	`RO`	`0x0`
27:12	`select`	defines the configurable bits of the base address field.	`RW`	`0x7F`
11:0	`low_fixed`	The minimum size of a region is limited to 4Kbytes	`RO`	`0xFFF`