L4_sys_scr Summary

L4_SYS Security Control Registers (SCR)

Base Address: 0x10D21100


Register Address Offset	Bit Fields
`noc_fw_l4_sys__ocp_slv__10d21100__l4_sys_scr`
`dma_ecc` `0x8` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac0rx_ecc` `0x12` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac0tx_ecc` `0x16` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac1rx_ecc` `0x20` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac1tx_ecc` `0x24` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac2rx_ecc` `0x28` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`emac2tx_ecc` `0x32` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`nand_ecc` `0x44` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`nand_read_ecc` `0x48` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`nand_write_ecc` `0x52` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`ocram_ecc` `0x56` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`sdmmc_ecc` `0x64` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`usb0_ecc` `0x68` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`usb1_cacheecc` `0x72` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`clock_manager` `0x76` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`io_manager` `0x84` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`reset_manager` `0x88` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`system_manager` `0x92` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`osc0_timer` `0x96` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`osc1_timer` `0x100` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`watchdog0` `0x104` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`watchdog1` `0x108` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`watchdog2` `0x112` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`watchdog3` `0x116` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`dap` `0x120` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_4` `RO 0x0`						`etr` `RW 0x0`	`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`watchdog4` `0x124` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_5` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_4` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_3` `RO 0x0`						`dmam1` `RW 0x0`	`dma` `RW 0x0`	`Reserved_1` `RO 0x0`							`mpu` `RW 0x0`
`power_manager` `0x128` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`usb1_rxecc` `0x132` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`usb1_txecc` `0x136` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`l4_noc_probes` `0x144` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`
`l4_noc_qos` `0x148` 32-bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved_3` `RO 0x0`							`axi_ap` `RW 0x0`	`Reserved_2` `RO 0x0`							`fpga2soc` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved_1` `RO 0x0`															`mpu` `RW 0x0`