dap 

         Per-Master Security bit for dap
Module Instance Base Address Register Address
noc_fw_l4_sys__ocp_slv__10d21100__l4_sys_scr 0x10D21100 0x10D21178

Size: 32

Offset: 0x78

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_4

RO 0x0

etr

RW 0x0

axi_ap

RW 0x0

Reserved_2

RO 0x0

fpga2soc

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

mpu

RW 0x0

dap Fields

Bit Name Description Access Reset
31:26 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
25 etr 
Security bit configuration for transactions from etr to dap. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
24 axi_ap 
Security bit configuration for transactions from axi_ap to dap. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
23:17 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
16 fpga2soc 
Security bit configuration for transactions from fpga2soc to dap. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0
15:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 mpu 
Security bit configuration for transactions from mpu to dap. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.
 RW 0x0