Intel High Level Synthesis Compiler Pro Edition: Version 20.4 Release Notes
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 20.4 |
1. Intel High Level Synthesis Compiler Pro Edition Version 20.4 Release Notes
The Intel® High Level Synthesis Compiler Pro Edition Release Notes provide late-breaking information about the Intel® High Level Synthesis Compiler Pro Edition Version 20.4.
For the most recent Standard Edition release notes, see the Intel® High Level Synthesis Compiler Standard Edition Release Notes .
About the Intel® HLS Compiler Pro Edition Documentation Library
| Title and Description | |
|---|---|
|
Release
Notes
Provide late-breaking information about the Intel® HLS Compiler. |
Link |
|
Getting Started
Guide
Get up and running with the Intel® HLS Compiler by learning how to initialize your compiler environment and reviewing the various design examples and tutorials provided with the Intel® HLS Compiler. |
Link |
|
User Guide
Provides instructions on synthesizing, verifying, and simulating intellectual property (IP) that you design for Intel FPGA products. Go through the entire development flow of your component from creating your component and testbench up to integrating your component IP into a larger system with the Intel Quartus Prime software. |
Link |
|
Reference
Manual
Provides reference information about the features supported by the Intel HLS Compiler. Find details on Intel® HLS Compiler command options, header files, pragmas, attributes, macros, declarations, arguments, and template libraries. |
Link |
|
Best Practices
Guide
Provides techniques and practices that you can apply to improve the FPGA area utilization and performance of your HLS component. Typically, you apply these best practices after you verify the functional correctness of your component. |
Link |
|
Quick
Reference
Provides a brief summary of Intel HLS Compiler declarations and attributes on a single two-sided page. |
Link |
1.1. New Features and Enhancements
The Intel® High Level Synthesis Compiler Pro Edition Version 20.4 includes the following new features:
-
Added
support for
Cyclone® V devices.
Cyclone® V device support in Intel® HLS Compiler Pro Edition requires Intel® Quartus® Prime Standard Edition or Intel® Quartus® Prime Lite Edition.
1.2. Changes in Software Behavior
- This release contains no changes in software behavior.
1.3. Intel High Level Synthesis Compiler Pro Edition Prerequisites
For detailed instructions about installing Intel® Quartus® Prime Pro Edition software, including system requirements, prerequisites, and licensing requirements, see Intel® FPGA Software Installation and Licensing .
The Intel® HLS Compiler requires the following software in addition to Intel® Quartus® Prime:
C++ Compiler
On Linux, Intel® HLS Compiler requires GCC 9.1.0 including the GNU C++ library and binary utilities (binutils).
This version of GCC is provided as part of your Intel® HLS Compiler installation. After installing the Intel® HLS Compiler, GCC 9.1.0 is available in <quartus_installdir>/gcc.
- Microsoft* Visual Studio* 2017 Professional
- Microsoft* Visual Studio* 2017 Community
Mentor Graphics* ModelSim* Software
- ModelSim* - Intel® FPGA Edition
- ModelSim* - Intel® FPGA Starter Edition
On Red Hat* Linux systems, ModelSim* software requires the Red Hat* development tools packages. Additionally, any 32-bit versions of ModelSim* software (including those provided with Intel® Quartus® Prime) require additional 32-bit libraries. The commands to install these requirements are provided in Installing the Intel® HLS Compiler on Linux Systems.
On SUSE* Linux systems, you must use your own licensed version of Mentor Graphics* ModelSim* software.
For information about all the ModelSim* software versions that the Intel® software supports, refer to the EDA Interface Information section in the Software and Device Support Release Notes for your edition of Intel® Quartus® Prime Pro Edition
1.4. Known Issues and Workarounds
This section provides information about known issues that affect the Intel® HLS Compiler Pro Edition Version 20.4.
| Description | Workaround |
|---|---|
|
(Windows only) Compiling a design in a directory with a long path name can result in compile failures. |
Compile the design in a directory with a short path name. |
| (Windows only) A long path for your Intel® Quartus® Prime installation directory can prevent you from successfully compiling and running the Intel® HLS Compiler tutorials and example designs. | Move the tutorials and examples to a short path name before trying to run them. |
| Libraries that target
OpenCL*
and are written in HLS cannot use streams or
pipes as an interface between
OpenCL*
code and the library written in HLS. However, the library in HLS can use streams or pipes if both endpoints are within the library (for example, a stream that connects two task functions). |
N/A |
| Libraries that target OpenCL* and are written in HLS might cause OpenCL* kernels that include the library to have a more conservative incremental compilation. | N/A |
|
When developing a library, if you have a
#define defining a value that
you use later in a #pragma, the
fpga_crossgen command fails. For example, the following code cannot be
compiled by the fpga_crossgen
command:
#define unroll_factor 5
int foo(int array_size) {
int tmp[100];
int sum =0;
//pragma unroll unroll_factor
#pragma ivdep array(tmp) safelen(unroll_factor)
for (int i=0;i<array_size;i++) {
sum+=tmp[i];
}
return sum;
}
|
Use __pragma instead of #pragma. For example, the following
compiles successfully with the fpga_crossgen
command:
#define unroll_factor 5
int foo(int array_size) {
int tmp[100];
int sum =0;
//pragma unroll unroll_factor
__pragma ivdep array(tmp) safelen(unroll_factor)
for (int i=0;i<array_size;i++) {
sum+=tmp[i];
}
return sum;
}
|
| When you use the -c command option to have separate compilation and linking stages in your workflow, and if you do not specify the -march option in the linking stage (or specify a different -march option value), your linking stage might fail with or without error messages. | Ensure that you use the same -march option value for both the compilation with the -c command option stage and the linking stage. |
Applying the hls_merge memory attribute to an array declared within
an unrolled or partially unrolled loop causes copies of the array to
be merged across the unrolled loop iterations.#pragma unroll 2
for (int I = 0; I < 8; i++) {
hls_merge(“WidthMerged”, “width”) int MyMem1[128];
hls_merge(“WidthMerged”, “width”) int MyMem2[128];
...
hls_merge(“DepthMerged”, “depth”) int MyMem3[128];
hls_merge(“DepthMerged”, “depth”) int MyMem4[128];
...
}
|
Avoid using the hls_merge memory attribute in unrolled
loops. If you need to merge memories in an unrolled loop, explicitly declare an array of struct type for width merging, or declare a deeper array for depth merging. struct Type {int A; int B;};
#pragma unroll 2
for (int I = 0; I < 8; i++) {
Type WidthMerged[128]; // Manual width merging
...
int DepthMerged[256]; // Manual depth merging
...
}
|
| In the Function Memory Viewer high-level design report, some function-scoped memories might appear as "optimized away". | None. When a file contains functions that are components and functions that are not components, all function-scoped variables are listed in the Function Memory List pane, but only variables from components have information about them to show in the Function Memory View pane. |
| Some high-level design reports fail in Microsoft* Internet Explorer*. | Use one of the following browsers
to view the reports:
|
The Loop Viewer in the High-Level Design
Reports has the following restrictions:
|
None. |
| Links in some reports in the High-Level Design Reports generated on Windows systems do not work. | Generate the High-Level Design Reports (that is, compile your code) on a Linux system. |
|
Using a struct of a single ac_int data type in steaming interface that uses
packets (ihc::usesPackets<true>) does not work. For example, the following code snippet does
not
work:
// class definition
class DataType {
ac_int<155, false> data;
...
}
// stream definition
typedef ihc::stream_in<DataType,
ihc::usesPackets<true>,
ihc::usesEmpty<true>
> DataStreamIn;
|
To use this combination in your
design, obey the following restrictions:
|
When running
a high-throughput simulation of your component using enqueue
function calls, if you do not use the ihc_hls_component_run_all function to run the enqueued
component calls after all of the ihc_hls_enqueue calls for that component, the
following behaviors occur:
|
Ensure that you use the ihc_hls_component_run_all function after all of the ihc_hls_enqueue calls for that component to run enqueued component function calls. |
|
Launching a task function with ihc::launch_always_run strips away optimization
attributes applied to the task function. In the
following code example, the attribute applied to the function is
ignored. The High-Level Design Reports show an II of 1 for this
task instead of the requested II of
4.
hls_component_ii(4) void noop()
{
bool sop, eop;
int empty;
auto const data = data_in.read(sop, eop, empty);
data_out.write(data, sop, eop, empty);
}
component void main_component()
{
ihc::launch<noop>();
}
|
To avoid stripping away the optimization, add a
while(1) loop to the affected
function apply the corresponding control pragma to the while(1) loop instead of the
function. The following code example show how
you can implement this change for the earlier code
example:
void noop()
{
#pragma ii 4
while (1)
{
bool sop, eop;
int empty;
auto const data = data_in.read(sop, eop, empty);
data_out.write(data, sop, eop, empty);
}
}
component void
main_component()
{
ihc::launch_always_run<noop>();
}
|
|
Only when simulating your component, the startofpacket signal of a stream
interface might behave incorrectly in simulation in some rare
situations that involve non-power-of-2 wide streams. Generated hardware does not have this issue. |
If you encounter this issue, pad your stream to a power-of-two width for simulation. |
|
For
Cyclone® V projects that contain
multiple HLS components, when you use the i++ command to compile your project to hardware
(i++ -march=CycloneV), you
might receive an error. While the error text differs depending on your project, the error signature is an Intel® Quartus® Prime compilation failure due to bad Verilog syntax. A module tries to use a function that the Intel® Quartus® Prime compiler cannot find. |
If you encounter this issue, put each HLS component in a separate project. |
|
When you specify the -ghdl=1
option of the i++ command, the
simulation of your component can fail. Specifying this option does not affect the generated RTL. The option affects only the generated simulation script. |
When compiling your design for simulation,
specify the ‑ghdl option
instead. When you use this option, you prevent your simulation from failing, but this option results in a larger simulation waveform. |
1.5. Software Issues Resolved
The following issues were corrected or otherwise resolved in the Intel® HLS Compiler Pro Edition Version 20.4.
| Customer Service Request Numbers | ||||||
|---|---|---|---|---|---|---|
| 00514931 | ||||||
1.6. Intel High Level Synthesis Compiler Pro Edition Release Notes Archives
1.7. Document Revision History for Intel HLS Compiler Pro Edition Version 20.4 Release Notes
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2021.01.08 | 20.4 |
|
| 2020.12.14 | 20.4 |
|