Product Collection
Stratix® V GX FPGA
Status
Launched
Launch Date
2010
Lithography
28 nm

Resources

Logic Elements (LE)
420000
Adaptive Logic Modules (ALM)
158500
Adaptive Logic Module (ALM) Registers
634000
Fabric and I/O Phase-Locked Loops (PLLs)
24
Maximum Embedded Memory
41.84 Mb
Digital Signal Processing (DSP) Blocks
256
Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP)
Hard Memory Controllers
No
External Memory Interfaces (EMIF)
DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3

I/O Specifications

Maximum User I/O Count
696
I/O Standards Support
3.0 V LVTTL, 1.2 V to 3.0 V LVCMOS, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, BLVDS
Maximum LVDS Pairs
348
Maximum Non-Return to Zero (NRZ) Transceivers
36
Maximum Non-Return to Zero (NRZ) Data Rate
14.1 Gbps
Transceiver Protocol Hard IP
PCIe Gen3

Package Specifications

Package Options
F1152, F1517

Supplemental Information

Additional Information