Product Collection
MAX® II CPLD
Status
Launched
Launch Date
Q1'14
Lithography
180 nm

Resources

Equivalent Macrocells
192
Pin-to-pin Delay
7.5 ns
User Flash Memory
8 Kb

Features

Boundary-scan JTAG
Yes
JTAG ISP
Yes
Fast Input Registers
Yes
Programmable Register Power-up
Yes
JTAG Translator
Yes
Real-time ISP
Yes
MultiVolt I/Os†
1.5, 1.8, 2.5, 3.3
I/O Power Banks
2
Maximum Output Enables
80
LVTTL/LVCMOS
Yes
Schmitt Triggers
Yes
Programmable Slew Rate
Yes
Programmable Pull-up Resistors
Yes
Programmable GND Pins
Yes
Open-drain Outputs
Yes
Bus Hold
Yes

Package Specifications

Package Options
M100, F100, T100
Package Size
6mm x 6mm, 11mm x 11mm, 16mm x 16mm

Supplemental Information

Additional Information