Marketing Status
Launched
Launch Date
Q2'19
Expected Discontinuance
1
Lithography
10 nm
Use Conditions
Base Transceiver Station

Resources

Logic Elements (LE)
2692760
Adaptive Logic Modules (ALM)
912800
Adaptive Logic Module (ALM) Registers
3651200
Fabric and I/O Phase-Locked Loops (PLLs)
28
Maximum Embedded Memory
287 Mb
Maximum High Bandwidth Memory (HBM)
1 GB
Digital Signal Processing (DSP) Blocks
8528
Digital Signal Processing (DSP) Format
Bfloat, Block Floating Point, Floating Point (hard IP), Multiply, Multiply and Accumulate, Variable Precision
Hard Processor System (HPS)
Quad-core 64 bit Arm* Cortex*-A53
Hard Crypto Blocks
1
Hard Memory Controllers
Yes
External Memory Interfaces (EMIF)
DDR II+, DDR2 SDRAM, DDR4, QDR IV
User-Flashable Memory
Yes
Internal Configuration Storage
Yes

I/O Specifications

Maximum User I/O Count
624
I/O Standards Support
1.2 V LVCMOS, 1.8 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, True Differential Signaling
Maximum LVDS Pairs
312
Maximum Non-Return to Zero (NRZ) Transceivers
24
Maximum Non-Return to Zero (NRZ) Data Rate
28.9 Gbps
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers
12
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate
57.8 Gbps
Transceiver Protocol Hard IP
PCIe Gen1, PCIe Gen2

Advanced Technologies

Hyper-Registers
Yes
FPGA Bitstream Security
Yes
Analog-to-Digital Converter
Yes

Package Specifications

Package Options
R2581A

Supplemental Information

Datasheet
Additional Information