Intel® FPGA IP Certifications

Intel is committed to providing intellectual property (IP) cores that work seamlessly with Intel® FPGA tools or interface specifications, making it easier for users to complete their designs quickly and easily. Intel may award IP cores one or more of the following certifications.

Platform Designer Compliant

The Platform Designer compliant certification is awarded to intellectual property (IP) cores that seamlessly integrate with the Platform Designer included in the Quartus® II or Intel® Quartus Prime design software. Platform Designer compliant cores support industry-standard interconnect interfaces including Avalon® Memory-Mapped (Avalon-MM), Avalon Streaming (Avalon-ST), ARM* AXI3*, AXI4*, AXI4-lite*, AXI4 Stream*, APB*, and AHB*.

Availability

Visit the online IP catalog for an up-to-date list of Platform Designer Compliant IP cores.

Platform Designer Compliant IP Core Deliverables

An IP core must meet the following requirements to achieve the Platform Designer compliant certification:

  • Interface to the system interconnect fabric via one of the industry-standard interconnect interfaces listed above
  • Platform Designer plug-and-play integration via hw.tcl

Intel FPGA Design Solutions Network members can certify their IP cores as Platform Designer compliant as long as they meet the above-mentioned requirements.

Verification Summary

Platform Designer compliant IP cores have been verified with an Avalon Monitor component on each Avalon-ST or Avalon-MM interface, and have no protocol violations.

Hardware Design Example

The IP core also includes a design example created with the Platform Designer, to illustrate the correct interaction of the IP core with the Platform Designer.

DSP Builder Ready

Intel awards the DSP Builder Ready certification to IP cores that have plug-and-play integration with the DSP Builder for Intel FPGAs software. The DSP Builder for Intel FPGAs shortens digital signal processing (DSP) design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. You can combine existing MATLAB/Simulink blocks with the DSP Builder for Intel FPGAs or Intel FPGA IP blocks to verify system-level specifications and generate hardware implementations. After installing DSP Builder Ready IP, a symbol appears in the Simulink library browser under the DSP Builder for Intel FPGAs Blockset.

I-Tested

In an increasingly competitive market, hardware designers must focus time and effort on designs that enhance and differentiate a product, rather than on designs that implement industry-standard protocols or interfaces. Drop-in intellectual property (IP) cores have, therefore, become a popular way to fulfill the need for standard protocol and interface logic. To ensure that an IP core meets the functional requirements of a complex protocol or the critical I/O timing requirements of an interface, hardware verification must be performed.

Intel® awards the interoperability-tested or I-Tested certification to Intel FPGA IP or Intel FPGA Design Solutions Network member IP cores that have been verified in an Intel FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the necessary protocols.

Availability

Visit the online IP catalog for an up-to-date list of I-Tested IP cores.

I-Tested Core Deliverables

Intel requires that the IP core have the following deliverables in order to achieve I-Tested certification:

  • Successful Interoperability Testing in an Intel FPGA on an Evaluation Board
  • The board must include other industry-standard components and/or off-board interfaces (e.g. to standard hardware test equipment) to verify the protocol managed by the IP core. The core must be tested at least with typical configurations and parameters and with typical performance targets.
  • Description of Hardware Platform
  • Core documentation must include a description of the hardware platform used, including the types of components used.
  • Documentation of Interoperability Test Process 
  • Core documentation must include descriptions of the tests performed. Details of test results may also be given, as appropriate.