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  1. Intel® Products
  2. Altera® FPGA, SoC FPGA and CPLD
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  4. Interface Protocols IP Cores
  5. Mobile Industry Processor Interface D-PHY IP

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MIPI D-PHY IP

Mobile Industry Processor Interface (MIPI) D-PHY is supported on Agilex™ 5 and Agilex™ 3 FPGAs allowing transmission and reception of data through PHY-protocol interface (PPI) to connect with camera serial interface (CSI) and display serial interface (DSI) applications.

  • Key Features
  • Applications
  • Documentation
  • Ordering Information

MIPI D-PHY

  • MIPI D-PHY feature supports high-speed (HS) and low-power (LP) modes and allows direct interface with the D-PHY compliance component without external components.

  • Supports low-power and high-speed signaling up to 3.5 Gbps* per lane.

  • Supports AXI-Lite interface for seamless video transmission and reception.

  • Enables unidirectional multi-lane configurations 1, 2, 4, or 8 lanes.

MIPI CSI-2

  • Latency Reduction and Transport Efficiency (LRTE) for image-sensor aggregation without adding to the overall system cost.
  • Differential Pulse Code Modulation (DPCM) compression for seamless compression of HD images for mission critical applications.
  • Reducing the number of wires in a system like IoT by using the Unified Serial Link (USL).
  • Scrambling reduces Power Spectral Density (PSD) emissions for longer channels.

MIPI DSI-2

  • High Resolution Support: MIPI DSI-2 supports high-resolution displays, including 4K, 5K UHD+, and 8K UHD resolutions
  • VESA Display Compression-M (VDC-M) Compliance: It is compliant with VESA VDC-M 1.2, supporting various encoding mechanisms like BP, transform, MPP, MPP fallback, and BP skip
  • Flexible Video Input Formats: Supports 8, 10, or 12 bits per component video, with 4:4:4 sampling for RGB and 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input formats
  • High Pixel Throughput: Capable of processing two pixels per clock per hard slice encoder, with parameterizable parallel slice encoder instances to adapt to different display resolutions

*Only in Agilex™ 5 FPGA E-Series Group A and D-Series devices.

  • 4K and 8K Image and Video Streaming.
  • Automotive – ADAS, In-Vehicle Infotainment, Electrification & Networking.
  • Sensor imaging and connectivity on UAV and Robotic Platforms.
  • Virtual Reality Headsets, Camera-enabled robots and drones.

Agilex™ 5 FPGAs - MIPI D-PHY IP User Guide

MIPI CSI-2 Intel® FPGA IP User Guide

 

IP

Included with the purchase of Quartus® Prime Design Software Ordering Codes

MIPI D-PHY IP

MIPI CSI-2 IP

MIPI DSI-2 IP

Yes No code needed
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