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  1. Intel® Products
  2. Altera® FPGA, SoC FPGA and CPLD
  3. Altera® FPGA Intellectual Property
  4. Interface Protocols IP Cores
  5. GTS Ethernet FPGA Hard IP

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GTS Ethernet FPGA Hard IP

Ethernet is ubiquitous across many markets and applications. The GTS Ethernet Intel FPGA Hard IP (EHIP) allows fast, flexible, and high-performance Ethernet implementation with minimal FPGA resource utilization. The EHIP includes a configurable, hardened protocol stack for Ethernet, compatible with the IEEE 802.3-2018 - IEEE Standard for Ethernet and the 25G/50G Ethernet Specification from the 25 Gigabit Ethernet Consortium.

GTS Ethernet Hard IP Connects an Increasing Number of Devices

Agilex™ 5 and Agilex™ 3 devices serve a broad range of applications that require high performance, lower power, and smaller form factors. These characteristics make them ideal for midrange FPGA applications across the edge and core including:

  • Wireless and wireline communications

  • Video and broadcast equipment

  • Industrial applications

  • Test and measurement products

  • Medical electronics

  • Data center

  • Defense applications

The majority of the applications listed above utilize Ethernet connectivity and can leverage the EHIP to help accelerate their designs.

  • Key Features
  • Documentation
  • Ordering Information
Features Agilex™ 5 FPGA Agilex™ 3 FPGA

Ethernet Rate/PMA combination

[Data Rate]-[Number of PMA]

  • 10GE-1
  • 25GE-1
  • 10GE-1
PMA Type
  • ETH MAC and OTN support on CH3 and CH2 per bank. All channels support PCS Direct and FlexE mode.
  • ETH MAC and OTN support on CH3 of the bank. All channels support PCS Direct and FlexE mode
Flexible Configuration
  • Media Access Control (MAC), Physical Coding Sublayer (PCS), and Physical Medium Attachment (PMA)
  • PCS and PMA with optional FEC supports:
    • Ethernet for Optical Transportation Network (OTN)
    • Flexible Ethernet (FlexE)
  • Media Access Control (MAC), Physical Coding Sublayer (PCS), and Physical Medium Attachment (PMA)
  • PCS and PMA with optional FEC supports:
    • Ethernet for Optical Transportation Network (OTN)
    • Flexible Ethernet (FlexE)

Client interface

  • MAC Avalon® streaming interface
  • PCS Direct Mode
    • Media Independent Interface (MII)
    • PCS66 – Supports OTN and FlexE mode
  • MAC Avalon® streaming interface
  • PCS Direct Mode
    • Media Independent Interface (MII)
    • PCS66 – Supports OTN and FlexE mode

Forward error correction (FEC)

  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 Reed-Solomon (RS) RS (528,514) (CL91)
  • IEEE 802.3 BASE-R Firecode (CL74)

Precision Timing and Link Training

  • Support for the 1588v2 Precision Time Protocol (PTP)
  • Support for Auto-negotiation (AN) and Link training (LT)
  • Support for the 1588v2 Precision Time Protocol (PTP)
  • Support for Auto-negotiation (AN) and Link training (LT)
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Agilex 5 FPGA: GTS Ethernet Intel® FPGA Hard IP User Guide

Agilex 5 FPGA: GTS Ethernet Intel® FPGA Hard IP Register Map

Agilex 3 FPGA: GTS Ethernet Intel® FPGA Hard IP User Guide

IP Included in Quartus® Prime Design Software Ordering Codes
GTS Ethernet Intel® FPGA Hard IP Yes No ordering code required
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Additional Resources

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Find the right Altera® FPGA Intellectual Property core for your needs.

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For technical support on this IP core, please visit Support Resources or Intel® Premier Support. You may also search for related topics on this function in the Knowledge Center and Communities.

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Evaluation mode and purchasing information for Altera® FPGA Intellectual Property cores.

IP Base Suite

Free Altera® FPGA IP Core licenses with an active license for Quartus® Prime Standard or Pro Edition Software.

Design Examples

Download design examples and reference designs for Altera® FPGA devices.

Contact Sales

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