Multi-Rate Ethernet PHY Intel® FPGA IP

The Multi-Rate Ethernet PHY Intel® FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration. This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.

Read the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® Stratix® 10 FPGA IP user guide ›

Read the Intel® Arria® 10 Transceiver PHY user guide ›

Read the Intel® Cyclone® 10 GX Transceiver PHY user guide ›

Read the V-Series Transceiver PHY IP core user guide ›

Multi-Rate Ethernet PHY Intel® FPGA IP

IP Quality Metrics

Basics

Year IP was first released

2017

First version of Intel Quartus Prime Software supported

16.1

Ordering code

IP-10GMRPHY

Status

Production

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim*-Intel FPGA Edition

Timing and/or layout constraints

Documentation with revision control

Readme file

Y

Any additional customer deliverables provided with IP

 

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for Intel FPGA IP Evaluation Mode Support

Y

Source language

Verilog

Testbench language

 

Software drivers provided

N

Driver operating system (OS) support

 

Implementation

User interface

XGMII (10G), GMII (1G)

IP-XACT metadata

N

Verification

Simulators supported

Mentor Graphics*, Synopsys*, Cadence*

Hardware validated

Intel Arria 10, Intel Stratix 10

Industry-standard compliance testing performed

N

If Yes, which test(s)?

 

If Yes, on which Intel FPGA device(s)?

 

If Yes, date performed

 

If No, is it planned?

N

Interoperability

IP has undergone interoperability testing

N

If yes, on which Intel FPGA device(s)

 

Interoperability reports available

N