Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration. This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G. It handles the frame encapsulation and flow of data between a client logic and Ethernet network via PCS and PMA (PHY).
Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration
- Datapath client interface:
- 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
- Management interface:
- Avalon® memory-mapped interface for PHY management
- Datapath Ethernet interface:
- 10M/100M/1G/2.5G/5G/10G (USXGMII)—Single 10.3125 Gbps serial link
Features
- Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard.
- Consists of a physical coding sublayer (PCS) function and an embedded physical medium attachment (PMA).
- Dynamically switchable PHY operating speed.
- 1G/2.5G, 2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G (MGBASE-T), 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M, 100M, 1G, 2.5G, 10G (MGBASE-T) operating modes.
- Users needing Copper-PHY capability for USXGMII, MGBASE-T modes will need to use an external PHY chip.
User Guides
Agilex™ 3 and Agilex™ 5 FPGAs and SoCs |
Agilex™ 7 FPGA (F-Tile) |
Stratix® 10 FPGA | Arria® 10 FPGA | Cyclone® 10 GX FPGA | Arria® V, Cyclone® V, Stratix® V FPGAs |
|---|---|---|---|---|---|
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