Offerings
Offering
ChevinID™ was designed by Chevin Technology using patented method (GB2609026) to add a further layer of protection to your Silicon supply chain by identifying malicious and accidental changes that can occur during the production process. ChevinID ™ authorizes and authenticates hardware and software functions, and establishes a secure root of trust, while allowing the selection, control and modification of features contained within encrypted envelopes of RTL netlists. ChevinID™ can be inserted into Silicon such as FPGA, ASIC, and SiP design with Chiplets.
Offering
Chevin Technology’s HMAC-SHA256 cryptographic accelerator function is used to securely generate and verify message authentication codes. Message authentication is increasingly required by corporations, government organizations, and individuals to secure communications between sender and receiver. The HMAC – SHA256 authentication function is especially suited for cybersecurity, defense, and aerospace applications, and can be added to existing products, or designed into prototypes. Contact us for more information, or to discuss source code and netlist licensing options for Intel® FPGAs and ASICs.
Offering
The TCP/IP (Transmission Control Protocol/ Internet Protocol) is an Ethernet IP stack for FPGAs that incorporates both the transport and internet layer protocols to deliver reliable, end to end network communications using the internet or on private networks. The TCP/ IP stack can be used with Chevin Technology’s 10G & 25G Ethernet IP cores for dependable, low-latency connectivity in any FPGA using a minimum of FPGA resources. Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technology’s TCP/IP offloads the TCP protocol using fast and efficient logic for checksum calculation. Valuable resources in your application are freed up by the TCP/IP which offloads the entire TCP stack onto FPGA logic. Using the FPGA to analyse packets instead of the CPU significantly increases data transfer time and consistently reduces jitter. The TCP/IP is easily integrated alongside other protocols to provide an easy path for the development of TCP enabled FPGA applications. Chevin Technology offer flexible licensing terms and engineering support packages to suit the requirements of each customer.
Offering
The UDP Protocol is a transport layer that runs on top of the Internet Protocol (IP) Layer and is used for connections where high sustained throughput is a priority and some data loss is expected, such as with video and audio streaming. Chevin Technology’s 10G & 25G UDP Ethernet IP core for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirming receipt. De-fragmentation is available as an option, so large UDP datagrams can be easily sent and received. The UDP IP core provides individual port numbers to differentiate between user requests, and receipt of data is verified using the checksum functionality. Chevin Technology’s 10G &25G UDP Ethernet IP core is configurable for Intel® & other FPGAs and simplifies integration by handling the complete Ethernet frame assembly. Chevin Technology’s UDP IP core is a mature IP core with proven success in customers’ projects. Reference designs are available for various boards to assist with integration and we offer our customers bespoke, expert engineering support packages to help meet their project goals. A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the user data payload is exchanged between the application and the UDP core. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi-port application is supported by a single UDP IP core by using the TDEST sideband embedded in the streaming interface.
Offering
The IEEE 802.3by compliant 10/25G MAC/PCS was designed in house at Chevin Technology, to provide an easy path to the integration of protocols such as TCP/IP and UDP protocols in your FPGA, whilst using minimal FPGA resources. The 10/25GMAC simplifies the synthesis of ultra-fast Duplex 25Gbit/s Ethernet for FPGAs. The 10/25GMAC IP core is a Low-Latency Ethernet MAC with a latency of 44.8ns in 2749 LUTs for 10Gbit/s and 20.5ns in 2680 LUTs for 25Gbit/s. When combined with the Low-Latency 10/25GPCS, the full packet round trip time for 10Gbit/s is ( MAC Input -> Wire -> MAC Output ) 153.8ns in 5153 LUTs; 25Gbit/s ( MAC Input -> Wire -> MAC Output ) is 128ns in 7930 LUTs.Chevin Technology offer a detailed user guide, expert support and design services to assist in the implementation of 10/25Gbit/s Ethernet connectivity in Intel® Agilex™ and other FPGAs. A reference design is available for technology partner Bittware’s IA-840F and IA-420F boards, as well as Alpha Data’s ADM-PCIE-8V3, ADM-PCE-9V3 boards. Flexible licensing terms are available with Chevin Technology IP cores, to allow for the unique requirements of each customers’ project. We understand that efficiency and reliability are crucial to our customers, and have created a powerful CRC32 checker & generator engine that checks the TX and RX data for errors, on a 64bit wide bus @ 390.625MHz.Latency of the 10/25GMAC can be reduced even further by the use of Cut-through mode; the first byte appears only 8 nanoseconds after arriving at 25GMII. Alternatively, the Store-and-Forward mode reduces application workload, as the 25GMAC drops all corrupt frames. The Frame Checksum verifies frame integrity; the CRC32 check result is available 8 nanoseconds after the final byte is received. The Deficit Idle Count optimizes the Inter Frame Gap (IFG) for absolute maximum Throughput and minimum Latency by maintaining an average IFG count.
Offering
Chevin Technology’s 10G/25G TCP/IP Offload Engine is an FPGA Synthesizable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. The TCP/IP Offload Engine provides a quick path to creating TCP enabled applications with a minimum of additional resources for network management at the FPGA side. The AXI4-Lite host interface permits control of the TCP’s registers and statistics for connection and link monitoring, and is routable per session. The TCP Offload Engine is highly configurable to optimize data exchange, power consumption and latency. The software driver allows users to easily manage features such as sending and receiving data to applications using DMAs (useful to implement higher level protocols); control routing and manage load balancing of the TCP to multiple applications; and to dynamically switch between AXI4 Streaming and AXI4 MM. By storing data and streaming from memory, the AXI4 Streaming and memory interface reduces power consumption by up to 2/3rds, as well as decreasing latency and complexity. The AXI4-Stream compliant user interface provides flow control, session identification and routing capabilities that offer seamless integration with system development and productivity tools such as Intel® Quartus® software / Intel® Platform Designer and others.