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MISSING LINK ELECTRONICS

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Missing Link Electronics (MLE) is a Silicon-Valley-based technology company with offices in Germany. We have been enabling key innovators in the automotive, industrial, test and measurement markets. MLE's mission is to develop and market technology solutions for Embedded Systems Realization via pre-validated IP and expert application support, and to combine off-the-shelf FPGA devices with Open-Source software for dependable, configurable embedded system platforms. MLE's solution for Intel comprise of mixed-signal FPGA technology, a direct and single-chip integration of analog I/Os, such as analog-to-digital converter (ADC) and digital-to-analog converter (DAC) into an Intel® FPGA. MLE supports Intel® FPGA customers to realize video and imaging processing systems, such as wireless transmitters for 3G-SDI full-HD video streaming. MLE also actively contributes to the Nios-II ecosystem.

Address

Industriestr. 10
Neu-Ulm, Bayern, 89231
Germany

Use Cases

High Performance Computing

Storage

Others

Industry

Communications : Telecommunications

Health and Life Sciences : Medical Imaging

Manufacturing : Automotive

Defense and Space

Company Resources

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Resource Type: Articles

Articles

Offerings

Offering

Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design

MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.

by MISSING LINK ELECTRONICS

Offering

100G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.

by MISSING LINK ELECTRONICS

Offering

100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP full accelerator for 50G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

Offering

10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

Offering

40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.

by MISSING LINK ELECTRONICS

Offering

40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

Offering

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

UDP/IP Full Accelerator for 50G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.

by MISSING LINK ELECTRONICS

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MISSING LINK ELECTRONICS

Mixed Signal FPGAs (ADC/DAC) - MLE FPGA IP Core Design

100G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

Low-Latency 10G Ethernet MAC - MLE FPGA IP Core Design

100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

50G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

10G/25G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

10G/25G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

40G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

40G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

50G UDP/IP Stack for Network Acceleration - MLE FPGA IP Core Design