Offerings
Offering
MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os embedded inside proven off-the-shelf FPGA devices.
Offering
UDP/IP Full Accelerator for 100G UDP/IP connections. Including UDP, IP, MAC Layer. Pipelined all-RTL implementation for ultra low latency.
Offering
The 10G Ethernet MAC IP Core from Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC) according to IEEE802.3 -2008 specification. The IP Core was specifically designed to have the lowest possible latency, and to be as resource efficient as possible at the same time.
Offering
TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.
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TCP/IP full accelerator for 50G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.
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TCP/IP Full Accelerator for 10G/25G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.
Offering
UDP/IP Full Accelerator for 10G/25G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.
Offering
TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low latency.
Offering
UDP/IP Full Accelerator for 40G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.
Offering
UDP/IP Full Accelerator for 50G UDP/IP connections. Including UDP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.