Offerings
Offering
The Rambus CSI-2 controller core is a second-generation MIPI CSI-2 core optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
Offering
The Rambus DSI-2 controller core is a second-generation MIPI DSI core optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
Offering
Part of a full suite of PCI Express (PCIe) controller add-on cores and drivers, the DMA Back-End Core provides high-performance, scatter gather DMA operation in a flexible fashion. It can be easily integrated and used in a wide variety of DMA-based systems.
Offering
Part of a full suite of PCI Express (PCIe) controller add-on cores and drivers, the AXI DMA Back-End Core provides high-performance, scatter gather DMA operation in a flexible fashion. It can be easily integrated and used in a wide variety of DMA-based systems.
Offering
Key Features: VESA® Display Stream Compression (DSC) 1.2b compliant, supports all DSC 1.2b mandatory and optional encoding mechanisms, backward compatible to DSC v1.1. Configurable maximum display resolution up to 8K (FUHD) • 8, 10, 12 bits per video component, YCbCr and RGB video output format • 4:4:4, 4:2:2, and 4:2:0 native coding , resilient to bitstream corruption, 3 pixels / clock internal processing architecture in 4:4:4 • 6 pixels / clock internal processing architecture in 4:2:2 and 4:2:0. Parameterizable number of parallel slice decoder instances(1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used. Automatic run time configuration of the number of parallel slice decoder instances in use • Support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® platform designer tool. Avalon memory-mapped interface for register access, PPS 128 bytes block decoding, Compliant solution for DisplayPort 1.4 or HDMI 2.1o compatibility for slices per line requirements. Supports flexible usage models and design architecture (inline decoding or panel frame buffer decoding).
Offering
Key Features: VESA® Display Stream Compression (DSC) 1.2b compliant, supports all DSC 1.2b mandatory and optional encoding mechanisms, backward compatible to DSC v1.1. Configurable maximum display resolution up to 8K (FUHD). 8, 10, 12 bits per video component YCbCr and RGB video output format 4:4:4, 4:2:2, and 4:2:0 native coding, 1 pixel / clock internal processing architecture in 4:4:4, 2 pixels / clock internal processing architecture in 4:2:2 and 4:2:0 .Parameterizable number of parallel slice encoder instances (1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used, support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® plaform designer tool. Avalon memory-mapped interface for register access. Compliant solution for DisplayPort 1.4™ or HDMI® 2.1o Compatibility for slices per line requirements when using a frame buffer ,supports flexible usage models and design architecture.
Offering
Key Features: VESA® Display Compression-M (VDC-M) 1.2 compliant. Supports all VDC-M encoding mechanisms o BP, transform, MPP, MPP fallback, and BP skip o Flatness detection and signaling. Configurable maximum display resolution of up to 16Kx16Ko Typical 4K (4096x2160), 5K UHD+, and 8K UHD supported, configurable compressed bit rate, in increments of 1/16 bitsper pixel (bpp) 8, 10, or 12 bits per component video 4:4:4 sampling for RGB video input format 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input formats Pixel throughput of two (2) pixels per clock per hard slice encoder. Parameterizable number of parallel slice encoder instances(1,2, 4, or 8) to adapt to the capability of the technology and target display resolutions used. Logical slice encoding (2 soft slices) in each physical encoder (hard slice), support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® platform designer tool, Avalon memory-mapped interface for register access. Compliant solution for MIPI® DSI-2SM v1.1. Supports flexible usage models and design architecture.