IEDM 2020 Marks Key Process and Packaging Innovations by Intel

Intel Shows Off a Full Pipeline of Innovations for Advancing the Future of Computing




Robert Chau

Intel Senior Fellow Director, Components Research

By Robert Chau

The International Electron Devices Meeting (IEDM), hosted every year since 1954 by the Institute of Electrical and Electronics Engineers (IEEE), is undoubtably the world’s premier conference for breakthrough semiconductor technologies. Intel researchers made 19 presentations at this week’s IEDM 2020, demonstrating breakthroughs in various next-generation process and packaging technologies including transistor technologies that increasingly focus on 3D architectures, paving the way for future technology nodes over the course of the next decade.

At Intel, innovation is driven by the dedication of hundreds of researchers who are intent on advancing growth opportunities in artificial intelligence, 5G network transformation, and the intelligent, autonomous edge for our customers. A decade ago, Intel met challenges in scaling and power consumption with the introduction the FinFET transistor, HK metal gate and strained silicon as the building blocks for moving semiconductor technology forward. At IEDM 2020, Intel demonstrated that it has a full pipeline of innovation that will be needed to deliver the building blocks of future world-changing technologies.

While FinFETs still have plenty of life, the industry will transition to a new architecture: Gate-All-Around (GAA) FETs, in which the gate wraps around the channel on all sides. GAA FETs pack more high-performance transistors into a given area, reducing the width of the standard cell as compared to a traditional FinFET. Another way to drive cell area scaling is through 3D vertical stacking of transistor devices. Whether GAA or FinFET, the height of a standard cell can be significantly decreased through monolithic stacking of a n-channel metal-oxide semiconductor (NMOS) device on top of a p-channel metal-oxide semiconductor (PMOS) device, or vice versa, and research in this 3D stacking is well underway at Intel.

Intel is pioneering a “self-aligned” process for these stacked devices that we believe is capable of lower manufacturing costs, with no thermal budget constraints compared to other approaches. In our presentation “3-D Self-aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” we detailed how a 50% area scaling benefit comes from combining stacked nanoribbon transistors and vertical interconnects between the two device layers. We believe it is the industry’s first practical demonstration of vertically stacked CMOS with multiple silicon nanoribbons.

We also described how strained transistor channels can be implemented into GAA transistors to improve their performance. Strained silicon is another industry breakthrough first brought into use by Intel, back during the 90-nanometer technology generation. Since then, pushing to higher strain levels has proven to be critical to keeping CMOS performance improvements on track. Our IEDM 2020 presentation details how strained channels can be implemented into GAA transistors with the use of high Ge-content silicon germanium technology to achieve high-performance PMOS devices.

Continuing to drive Moore’s Law scaling requires integrating new features from every aspect of the compute platform, not just at the silicon level. At IEDM ’19 we described research that extends our 3D stacked Foveros packaging technology. This year we demonstrated packaging innovations to support RF devices, critical for the 5G and 6G communications industry. At IEDM ’20 we introduced a method using lithography – rather than laser drilling – to create fine pitch vias in organic packages. Here, Intel has demonstrated the industry’s first low-loss multilayer organic package for integrated multiplexer and filter devices at sub-THz frequencies to further enable customers pursuing future 6G networks.

Following 2019’s IEDM, I wrote that Moore’s Law has been the guiding principle for the semiconductor industry for more than 50 years and its future is brighter than ever. A year later, following IEDM ’20, not only am I reassured about my previous statements, but now with more technology innovation in the pipeline than ever before, I am even more confident that Intel will lead the ecosystem to realize these innovations in our technologies.

Summary of Key Intel Innovations at IEDM 2020

  • Demonstration of a self-aligned 3D stacked multi-ribbon CMOS transistor architecture for increased density & continued Moore’s Law scaling.
  • Demonstration of high-performance short-channel Gate-All-Around (GAA) strained Si0.4Ge0.6 nanosheet PMOS transistor with a highly scaled Si-cap-free gate oxide for transistor performance enhancement.
  • Hafnia-based ferroelectric memory with industry-best endurance data demonstrated for future dense embedded memory applications.
  • Demonstration of integrated sub-THz devices on panel-level organic package substrate using a novel lithography defined vias process.
  • Demonstration of monolithic GaN NMOS/Si CMOS integration on 300mm Si wafer for single-chip fully integrated high-performance 5G/6G and power delivery applications.
  • Demonstration of an integrated on-die metal interconnect system with different metal aspect ratios, air gaps and geometries to boost interconnect RC performance.

Robert Chau is an Intel Senior Fellow and director of Components Research at Intel Corporation.

Photo: Robert Chau, Intel Senior Fellow in Technology Development, directs Intel’s Components Research team that invents and develops novel materials, devices, interconnects, patterning and packaging used in Intel technology. (Credit: Walden Kirsch/Intel Corporation)