To satisfy the ever-increasing demand for more computing power, Intel and many of our colleagues in the semiconductor industry have come to the same conclusion: The future of chip innovation lies in moving to modular designs based on “chiplet” building blocks, essentially moving from system-on-chip (SoC) to System-on-Package (SoP) chip architectures.
The feasibility of implementing complex systems on monolithic dies is reaching its physical and economic limits. Gordon Moore predicted this “Day of Reckoning” in his seminal 1965 white paper, “Cramming More Components Onto Integrated Circuits,” writing that as chip density and complexity progressed, eventually “it may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”
The industry’s increasing adoption of modular semiconductor design takes us into the realm of SoP, giving architects incredible flexibility to mix and match the best IP and process technologies for any given product. Intel has been shipping chiplet-based designs since 2016 with Intel® Stratix®10 FPGAs. Modular design is also a key component of our IDM 2.0 strategy as we use internal and external foundry resources to build our products while offering our foundry services to the industry. Later this year, our customers will see our next-generation tile-based processors in the Sapphire Rapids and Ponte Vecchio SoCs. The success of this future in semiconductor design hinges on there being open standards to enable interoperability throughout the semiconductor supply chain.
In its fullest expression, SoP, chiplet-based architectures allow designers to bring together design IP and process technologies from multiple vendors. But this level of modularity and design freedom will only work if designers are working from standardized, interoperable hardware. We’ve seen this approach work time and again with now-familiar industry specifications including PCIe, CXL and USB. The best way to achieve standardized hardware across multiple vendors is to set a single, open specification that everyone can design to.
That’s why this week, Intel joined forces with Advanced Semiconductor Engineering Inc. (ASE), AMD, Arm, Google Cloud, Meta, Microsoft Corp., Qualcomm Inc., Samsung and Taiwan Semiconductor Manufacturing Co. to launch the Universal Chiplet Interconnect Express (UCIe) consortium. The UCIe consortium is focused on a single goal: creating an open ecosystem for enabling chiplets designed and manufactured on different process technologies by different vendors to work together when integrated with advanced packaging technologies.
Chiplets give designers greater flexibility, open new frontiers for reuse and enable innovation on price, performance and power consumption across the compute continuum. Moore foresaw this day. Now, we believe chiplets are the key to extending Moore’s Law through the next decade and beyond. Our consortium colleagues agree. And we’ll get to the next set of computing breakthroughs faster if we begin by settling on a well-defined specification. With Intel’s experience building these systems, we were able to donate a mature spec to the consortium that gave us a starting place. After feedback from the other founding members, our working group quickly ratified a 1.0 specification that works for everyone.
Membership in the UCIe Consortium is open to all companies in the industry that want to help enhance the UCIe specification. We expect rapid uptake among our colleagues up and down the silicon value chain – and we encourage industry-wide participation in future UCIe specifications.
Moving to a chiplet architecture will bring other benefits to the industry, too. Customers will be able to leverage different manufacturers more easily for any component of their solutions, motivating manufacturers to deliver new levels of quality, price and customer service. Competition will take place on a level playing field, where products and services are the differentiators, not artificially constrained ecosystems or technological incumbency.
UCIe is a critical component of Intel’s IDM 2.0 strategy. This specification builds on Intel’s open Advanced Interface Bus (AIB) standard to allow unprecedented flexibility, a fast and cost-effective way to provide solutions, and the ability to use the right chiplet for the job, regardless of who makes it. Going forward, you’ll see more SoP designs that feature Intel silicon alongside chiplets from other foundries. It’s a new era of semiconductor architecture that puts designers in control and continues Moore’s vision of doubling computing power well into the foreseeable future. We couldn’t be prouder about helping bring this open ecosystem to life.
To find out more about the UCIe specification, download an evaluation license or become a member, go to the UCIe consortium website.
Kurt Lender is IO Technology Solution Team Strategist in the Datacenter and AI Group of Intel Corporation.