Serial ATA AHCI: Specification, Rev. 1.1
Serial ATA AHCI 1.1 Specification
Revision 1_1.doc
Serial TATAA
Serial A
Advanced Host Controller cInterfacee
Advanced Host Controller Interfa
I(AHCI)) (AHC
Revision .1.11
Revision 1
Revision 1_1.doc
Please send comments to Amber Huffman
amber.huffman@intel.com
i
Revision 1_1.doc
Table of Contents
1 INTRODUCTION ................................................................................................................ 1
1.1 Overview.........................................................................................................................................1
1.2 Scope..............................................................................................................................................1
1.3 Outside of Scope ............................................................................................................................1
1.4 Block Diagram ................................................................................................................................1
1.5 Conventions....................................................................................................................................3
1.6 Definitions.......................................................................................................................................4
1.6.1 command list ..........................................................................................................................................4
1.6.2 command slot.........................................................................................................................................4
1.6.3 cs............................................................................................................................................................4
1.6.4 D2H........................................................................................................................................................4
1.6.5 device.....................................................................................................................................................4
1.6.6 FIS..........................................................................................................................................................4
1.6.7 H2D........................................................................................................................................................4
1.6.8 HBA........................................................................................................................................................4
1.6.9 n/a ..........................................................................................................................................................4
1.6.10 port.........................................................................................................................................................4
1.6.11 PRD........................................................................................................................................................4
1.6.12 queue .....................................................................................................................................................4
1.6.13 register memory .....................................................................................................................................4
1.6.14 system memory......................................................................................................................................5
1.7 Theory of Operation........................................................................................................................5
1.8 Interaction with Legacy Software....................................................................................................5
1.9 References .....................................................................................................................................6
2 HBA CONFIGURATION REGISTERS................................................................................... 7
2.1 PCI Header.....................................................................................................................................7
2.1.1 Offset 00h: ID - Identifiers ......................................................................................................................7
2.1.2 Offset 04h: CMD - Command.................................................................................................................7
2.1.3 Offset 06h: STS - Device Status.............................................................................................................8
2.1.4 Offset 08h: RID - Revision ID .................................................................................................................8
2.1.5 Offset 09h: CC - Class Code..................................................................................................................8
2.1.6 Offset 0Ch: CLS – Cache Line Size .......................................................................................................8
2.1.7 Offset 0Dh: MLT – Master Latency Timer ..............................................................................................9
2.1.8 Offset 0Eh: HTYPE – Header Type........................................................................................................9
2.1.9 Offset 0Fh: BIST – Built In Self Test (Optional)......................................................................................9
2.1.10 Offset 10h – 20h: BARS – Other Base Addresses (Optional) ................................................................9
2.1.11 Offset 24h: ABAR – AHCI Base Address ...............................................................................................9
2.1.12 Offset 2Ch: SS - Sub System Identifiers ................................................................................................9
2.1.13 Offset 30h: EROM – Expansion ROM (Optional) ...................................................................................9
2.1.14 Offset 34h: CAP – Capabilities Pointer.................................................................................................10
2.1.15 Offset 3Ch: INTR - Interrupt Information ..............................................................................................10
2.1.16 Offset 3Eh: MGNT – Minimum Grant (Optional)...................................................................................10
2.1.17 Offset 3Fh: MLAT – Maximum Latency (Optional) ...............................................................................10
2.2 PCI Power Management Capabilities...........................................................................................10
2.2.1 Offset PMCAP: PID - PCI Power Management Capability ID...............................................................10
2.2.2 Offset PMCAP + 2h: PC – PCI Power Management Capabilities.........................................................10
2.2.3 Offset PMCAP + 4h: PMCS – PCI Power Management Control And Status........................................11
2.3 Message Signaled Interrupt Capability (Optional)........................................................................11
2.3.1 Offset MSICAP: MID – Message Signaled Interrupt Identifiers ............................................................11
2.3.2 Offset MSICAP + 2h: MC – Message Signaled Interrupt Message Control..........................................11
2.3.3 Offset MSICAP + 4h: MA – Message Signaled Interrupt Message Address ........................................12
2.3.4 Offset MSICAP + (8h or Ch): MD – Message Signaled Interrupt Message Data..................................12
2.3.5 Offset MSICAP + 8h: MUA – Message Signaled Interrupt Upper Address (Optional)..........................12
2.4 Serial ATA Capability (Optional)...................................................................................................12
2.4.1 Offset SATACAP: SATACR0 – Serial ATA Capability Register 0.........................................................12
2.4.2 Offset SATACAP + 4h: SATACR1 – Serial ATA Capability Register 1 ................................................12
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2.5 Other Capability Pointers..............................................................................................................13
3 HBA MEMORY REGISTERS ........................................................................................... 14
3.1 Generic Host Control ....................................................................................................................14
3.1.1 Offset 00h: CAP – HBA Capabilities.....................................................................................................14
3.1.2 Offset 04h: GHC – Global HBA Control................................................................................................16
3.1.3 Offset 08h: IS – Interrupt Status Register.............................................................................................17
3.1.4 Offset 0Ch: PI – Ports Implemented.....................................................................................................17
3.1.5 Offset 10h: VS – AHCI Version ............................................................................................................18
3.1.6 Offset 14h: CCC_CTL – Command Completion Coalescing Control....................................................18
3.1.7 Offset 18h: CCC_PORTS – Command Completion Coalescing Ports .................................................19
3.1.8 Offset 1Ch: EM_LOC – Enclosure Management Location ...................................................................19
3.1.9 Offset 20h: EM_CTL – Enclosure Management Control ......................................................................19
3.2 Vendor Specific Registers ............................................................................................................20
3.3 Port Registers (one set per port) ..................................................................................................20
3.3.1 Offset 100h: P0CLB –
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