These free resources are available to the Intel® Developer Network for PCI* Express Architecture community.
PCI Express* Specifications
The PHY Interface for the PCI Express* (PIPE) Architecture Revision 5.2 is an updated version of the PIPE spec that supports PCI Express*, SATA, USB, DisplayPort, and Converged I/O architectures.
The review draft PCI Express* Device Security Enhancements Specification Revision 0.71 defines PCIe* Device Firmware Measurement and PCIe* Device Authentication that enable a Host to query and verify the identity and capability of a PCIe* Device, to improve system security.
The Logical PHY Interface Specification, Revision 1.0 defines the interface between the link layer and the logical physical layer for PCI Express* and CXL architectures.
PCI Express* Resources
If you’re new to PCI Express*, check out content from the PCI-SIG*.
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