PCI Express* Architecture
These free resources are available to the Intel® Developer Network for PCI Express* Architecture community.
PCI Express* Specifications
By downloading and reading these documents, you agree to the obligations set forth in the Intel® Developer Network for PCI Express* Architecture user agreement.
The PHY Interface for the PCI Express* (PIPE) Architecture Revision 5.0 is an updated version of the PIPE spec that supports PCI Express, SATA, USB, DisplayPort, and Converged I/O architectures.
The review draft PCI Express Device Security Enhancements Specification Revision 0.5 defines PCIe Device Firmware Measurement and PCIe Device Authentication that enable a Host to query and verify the identify and capability of a PCIe Device to improve system security.
PCI Express* Resources
If you’re new to PCI Express*, check out content from the PCI-SIG*.
Read the PDF (744 KB) ›
White Papers
Tools
The SigTest* tool version 3.2.10 is a beta version of SigTest that supports M.2 SSIC module and system testing for M-PHY gear 1 and gear 2. ICTT will take waveform files as input in binary and text forms for most common oscilloscope formats.
- PCI Express* 4.0 Connector Measurement Board File
- PCI Express* 4.0 Connector High Speed Electrical Test Procedure
- PCI Express* 3.0 Connector High Speed Connector Evaluation Board (CEB) (ZIP 1.6MB)
- PCI Express* 3.0 Connector High Speed Electrical Test Procedure (ZIP 1.7MB)
- PCI Express* 3.0 Characterization Board Support Bracket Design (ZIP 334KB)
