PCI Express* Architecture
These free resources are available to the Intel® Developer Network for PCI* Express Architecture community.
PCI Express* Specifications
The PHY Interface for the PCI Express* (PIPE) Architecture Revision 5.2 is an updated version of the PIPE spec that supports PCI Express*, SATA, USB, DisplayPort, and Converged I/O architectures.
The review draft PCI Express* Device Security Enhancements Specification Revision 0.71 defines PCIe* Device Firmware Measurement and PCIe* Device Authentication that enable a Host to query and verify the identity and capability of a PCIe* Device, to improve system security.
The Logical PHY Interface Specification, Revision 1.0 defines the interface between the link layer and the logical physical layer for PCI Express* and CXL architectures.
PCI Express* Resources
If you’re new to PCI Express*, check out content from the PCI-SIG*.
Read the PDF (744 KB) ›
White Papers
Tools
In addition to the software and resources available through the PCI-SIG*, Intel has developed the procedures and design information below to assist in verifying connector suitability for use in systems implementing PCI Express*.
- PCI Express* 5.0 CEM Connector High Speed Electrical Test Procedure
- PCI Express* 5.0 Connector Measurement Board File
- PCI Express* 4.0 Connector Measurement Board File
- PCI Express* 4.0 Connector High Speed Electrical Test Procedure
- PCI Express* 3.0 Connector High Speed Connector Evaluation Board (CEB) (ZIP 1.6MB)
- PCI Express* 3.0 Connector High Speed Electrical Test Procedure (ZIP 1.7MB)
- PCI Express* 3.0 Characterization Board Support Bracket Design (ZIP 334KB)
