PCI Express* Architecture

These free resources are available to the Intel® Developer Network for PCI* Express Architecture community.

PCI Express* Specifications

The PHY Interface for the PCI Express* (PIPE) Architecture Revision 5.2 is an updated version of the PIPE spec that supports PCI Express*, SATA, USB, DisplayPort, and Converged I/O architectures.

The review draft PCI Express* Device Security Enhancements Specification Revision 0.71 defines PCIe* Device Firmware Measurement and PCIe* Device Authentication that enable a Host to query and verify the identity and capability of a PCIe* Device, to improve system security.

The Logical PHY Interface Specification, Revision 1.0 defines the interface between the link layer and the logical physical layer for PCI Express* and CXL architectures.

2-Wire Translator Component Spec DRAFT Revision 0.3, defines a component solution for PCI-Express* forwards/backwards compatibility of the sideband bus (SMBus/I3C).

PCI Express* Resources

If you’re new to PCI Express*, check out content from the PCI-SIG*.
Read the PDF (744 KB) ›

Compute Express Link™ (CXL) Resources

CXL-cache/mem Protocol Interface (CPI) specification, has been developed to map coherent protocols between an agent and a fabric.

Streaming Fabric Interface (SFI) Specification has been developed to map Load/Store protocols (like PCIe) between an agent and a fabric.

White Papers

Tools

In addition to the software and resources available through the PCI-SIG*, Intel has developed the procedures and design information below to assist in verifying connector suitability for use in systems implementing PCI Express*.

Related Videos

Show more Show less

<script>var isTargetEnabled =false;</script>

<script type="text/javascript">
    var cq_tms = {
        wa_rintelproduct: "rintelproduct:processors/serverprocessors/intelxeonprocessor5000sequence/intelxeonprocessor5500series",
        wa_emtsubject: "emtsubject:itinformationtechnology/hpchighperformancecomputing",
        
        wa_industry_type: "",
        wa_partner_prog: "",
        wa_subject: "emtsubject:itinformationtechnology/hpchighperformancecomputing",
        wa_biz_size: "",
        wa_emt_org: "emtorganizationalstructure:dcgdatacentergroup",
        wa_emt_intel: "",
        wa_partner_type: "",
        wa_programidentifier: "none",
        wa_location: "us",
        wa_language: "en",
        wa_english_title: "PCI Express* Architecture",
        wa_content_type: "landingpage",
        wa_intel_platform: "",
        wa_applications: "",
        wa_local: "en_US",
        wa_intel_technology: "",
        wa_system_type: "",
        wa_product_name: "rintelproduct:processors/serverprocessors/intelxeonprocessor5000sequence/intelxeonprocessor5500series",
        wa_audience: "emtaudience:business/btssbusinesstechnologysolutionspecialist/hardwareengineer",
        wa_life_cycle: "",
        wa_cq_url: "/content/www/us/en/io/pci-express/pci-express-architecture-devnet-resources.html",
        wa_page_type_micro: "mf-contentdetailpage",
        wa_env: "prd",
        wa_cq_pub_env: "publish",
        wa_transl_status: "",
        wa_product_id: "39565",
        wa_software: "",
        wa_reference_design: "",
        wa_codename: "",
        wa_created_date: "1311933180285",
        wa_modifed_date: "1585689348302",
        wa_ownedby: "emtorganizationalstructure:dcgdatacentergroup,emtorganizationalstructure:dcgdatacentergroup",
        wa_managedby: "emtorganizationalstructure:dcgdatacentergroup,emtorganizationalstructure:smgsalesandmarketinggroup/smgcxssmgcustomerexperienceandscalegroup",
        wa_idz_nid : "",
        wa_event_type: "",
        wa_idz_custom_tags: "",
        wa_programming_language: "",
        wa_skill_level: "",
        wa_solution: "",
        wa_product_formFactor: "",
        wa_operating_system: "",
        wa_marketing_products: "",
        wa_ssg_third_party_prod_sys_sol: "",
        wa_intel_prd_levels: '[{"level4":{"id":"39565","desc":"intelxeonprocessor5500series"},"level1":{"id":"873","desc":"processors"},"level3":{"id":"28144","desc":"intelxeonprocessor5000sequence"},"productCategory":"rintelproduct","level2":{"id":"83421","desc":"serverprocessors"}}]',
        
        wa_secondary_content_type: ""
    };
    
    
    
    cq_tms.wa_tms_sync_load = "deferred";
    
</script>

<script type="text/javascript" src="/content/dam/www/global/wap/tms.sync.js" async></script>

<link rel="stylesheet" href="/etc/designs/ver/6.8.1152/intel/clientlibs/pages/commons-page.min.css" type="text/css"><script src="/etc/designs/ver/6.8.1152/intel/clientlibs/pages/commons-page.min.js" defer></script>

<link rel="stylesheet" href="/etc/designs/ver/6.8.1152/intel/clientlibs/pages/contact-us.min.css" type="text/css">

<script>!function(){var e=setInterval(function(){"undefined"!=typeof $CQ&&($CQ(function(){CQ_Analytics.SegmentMgr.loadSegments("/etc/segmentation"),CQ_Analytics.ClientContextUtils.init("/etc/clientcontext/intel",window.location.pathname.substr(0,window.location.pathname.indexOf(".")))}),clearInterval(e))},100)}();</script>

<link rel="stylesheet" type="text/css" href="/etc/designs/intel/us/en/css/intel.rwd.override.css"/>