PCI Express* Architecture

These free resources are available to the Intel® Developer Network for PCI* Express Architecture community.

PCI Express* (PCIe) Specifications

The PHY Interface for the PCI Express* (PIPE) Architecture Revision 5.2 is an updated version of the PIPE spec that supports PCI Express*, SATA, USB, DisplayPort, and Converged I/O architectures.

The Logical PHY Interface Specification, Revision 1.0 defines the interface between the link layer and the logical physical layer for PCI Express* and CXL architectures.

The LPIF Adapter for Die-to-Die Interconnect Revision 0.5 outlines implementation guidelines for using the Logical PHY Interface (LPIF) for die-to-die transport.

2-Wire Translator Component Spec DRAFT Revision 0.3 defines a component solution for PCI-Express forward/backward compatibility of the sideband bus (SMBus/I3C).

The PCI Express* Device Security Enhancements Specification is deprecated and is not recommended for new implementations. Instead, please refer to the Security Protocol and Data Model (SPDM) Specification (https://www.dmtf.org/dsp/DSP0274) and Component Measurement and Authentication (CMA) & Data Object Exchange (DOE) ECNs (https://pcisig.com/specifications).

PCI Express* Resources

If you’re new to PCI Express*, check out content from the PCI-SIG*.
Read the PDF (744 KB) ›

Compute Express Link™ (CXL) Resources

CXL-cache/mem Protocol Interface (CPI) specification, has been developed to map coherent protocols between an agent and a fabric.

Streaming Fabric Interface (SFI) Specification has been developed to map Load/Store protocols (like PCIe) between an agent and a fabric.

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