Variable Precision DSP Blocks User Guide: Agilex™ 3 FPGAs and SoCs

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ID 849313
Date 8/06/2025
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 3 Variable Precision DSP Blocks Overview 2. Agilex™ 3 Variable Precision DSP Blocks Architecture 3. Agilex™ 3 Variable Precision DSP Blocks Operational Modes 4. Agilex™ 3 Variable Precision DSP Blocks Design Considerations 5. Native Fixed Point DSP Agilex FPGA IP References 6. Native Floating Point DSP Agilex FPGA IP References 7. Native AI Optimized DSP Agilex™ FPGA IP References 8. Multiply Adder FPGA IP References 9. ALTMULT_COMPLEX FPGA IP References 10. LPM_MULT FPGA IP References 11. LPM_DIVIDE (Divider) FPGA IP References 12. Document Revision History for the Variable Precision DSP Blocks User Guide: Agilex™ 3 FPGAs and SoCs
1. Agilex™ 3 Variable Precision DSP Blocks Overview x
1.1. Features 1.2. Supported Operational Modes in Agilex™ 3 Devices
1.2. Supported Operational Modes in Agilex™ 3 Devices x
1.2.1. Fixed-point Arithmetic 1.2.2. Floating-point Arithmetic
2. Agilex™ 3 Variable Precision DSP Blocks Architecture x
2.1. Fixed-point Arithmetic 2.2. Floating-point Arithmetic 2.3. Tensor Mode
2.1. Fixed-point Arithmetic x
2.1.1. Input Register Bank for Fixed-point Arithmetic 2.1.2. Pipeline Registers for Fixed-point Arithmetic 2.1.3. Pre-adder for Fixed-point Arithmetic 2.1.4. Internal Coefficient for Fixed-point Arithmetic 2.1.5. Multipliers for Fixed-point Arithmetic 2.1.6. Adder or Subtractor for Fixed-point Arithmetic 2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic 2.1.8. Systolic Register for Fixed-point Arithmetic 2.1.9. Double Accumulation Register for Fixed-point Arithmetic 2.1.10. Output Register Bank for Fixed-point Arithmetic
2.2. Floating-point Arithmetic x
2.2.1. Input Register Bank for Floating-point Arithmetic 2.2.2. Pipeline Registers for Floating-point Arithmetic 2.2.3. Multipliers for Floating-point Arithmetic 2.2.4. Adder or Subtractor for Floating-point Arithmetic 2.2.5. Output Register Bank for Floating-point Arithmetic 2.2.6. Exception Handling for Floating-point Arithmetic
3. Agilex™ 3 Variable Precision DSP Blocks Operational Modes x
3.1. Operational Modes for Fixed-point Arithmetic 3.2. Operational Modes for Floating-point Arithmetic 3.3. Operational Modes for Tensor Mode
3.1. Operational Modes for Fixed-point Arithmetic x
3.1.1. Independent Multiplier Mode 3.1.2. Multiplier Adder Sum Mode 3.1.3. Independent Complex Multiplier 3.1.4. Systolic FIR Mode
3.1.1. Independent Multiplier Mode x
3.1.1.1. 18 × 18 or 18 × 19 Independent Multiplier 3.1.1.2. 27 × 27 Independent Multiplier
3.1.2. Multiplier Adder Sum Mode x
3.1.2.1. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 6 Mode
3.1.2.1. 8 x 8 (Unsigned) or 9 x 9 (Signed) Sum of 6 Mode x
3.1.2.1.1. 18 × 19 Multiplication Summed with 36-Bit Input Mode
3.1.4. Systolic FIR Mode x
3.1.4.1. Mapping Systolic Mode User View to Variable Precision Block Architecture View 3.1.4.2. 18-bit Systolic FIR Mode 3.1.4.3. 27-Bit Systolic FIR Mode
3.2. Operational Modes for Floating-point Arithmetic x
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions 3.2.2. FP16 Half-precision Floating-point Arithmetic Functions 3.2.3. Multiple Floating-point Variable DSP Blocks Functions
3.2.1. FP32 Single-precision Floating-point Arithmetic Functions x
3.2.1.1. FP32 Multiplication Mode 3.2.1.2. Adder or Subtract Mode 3.2.1.3. Multiply Accumulate Mode 3.2.1.4. FP32 Vector One Mode 3.2.1.5. FP32 Vector Two Mode
3.2.2. FP16 Half-precision Floating-point Arithmetic Functions x
3.2.2.1. FP16 Supported Precision Formats 3.2.2.2. Sum of Two FP16 Multiplication Mode 3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode 3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode 3.2.2.5. FP16 Vector One Mode 3.2.2.6. FP16 Vector Two Mode 3.2.2.7. FP16 Vector Three Mode
3.2.3. Multiple Floating-point Variable DSP Blocks Functions x
3.2.3.1. Multiply-Add or Multiply-Subtract Mode 3.2.3.2. Direct Vector Dot Product 3.2.3.3. Complex Multiplication
3.3. Operational Modes for Tensor Mode x
3.3.1. Data Input Feed Preloading Method 3.3.2. Side Input Feed Preloading Method 3.3.3. Tensor Floating-point Mode 3.3.4. Tensor Fixed-point Mode 3.3.5. Tensor Accumulation Mode
3.3.3. Tensor Floating-point Mode x
3.3.3.1. Input Register Bank for Tensor Floating-point Mode 3.3.3.2. Pipeline Registers for Tensor Floating-point Mode 3.3.3.3. Cascade Signals for Tensor Floating-point Mode 3.3.3.4. Output Registers for Tensor Floating-point Mode
3.3.4. Tensor Fixed-point Mode x
3.3.4.1. Input Register Bank for Tensor Fixed-point Mode 3.3.4.2. Pipeline Registers for Tensor Fixed-point Mode 3.3.4.3. Cascade Signals for Tensor Fixed-point Mode 3.3.4.4. Output Registers for Tensor Fixed-point Mode
3.3.5. Tensor Accumulation Mode x
3.3.5.1. Input Register Bank for Tensor Accumulation Mode 3.3.5.2. Pipeline Registers for Tensor Accumulation Mode 3.3.5.3. Cascade Signals for Tensor Accumulation Mode 3.3.5.4. Output Registers for Tensor Accumulation Mode
4. Agilex™ 3 Variable Precision DSP Blocks Design Considerations x
4.1. Fixed-point Arithmetic 4.2. Floating-point Arithmetic 4.3. DSP Block Cascade Limit in Agilex™ 3 Devices
4.1. Fixed-point Arithmetic x
4.1.1. Configurations for Input, Pipeline, and Output Registers 4.1.2. Internal Coefficient and Pre-Adder for Fixed-point Arithmetic 4.1.3. Accumulator for Fixed-point Arithmetic 4.1.4. Input Cascade for Fixed-point Arithmetic 4.1.5. Chainout Adder/Accumulator Feature
4.1.1. Configurations for Input, Pipeline, and Output Registers x
4.1.1.1. Restrictions for Input Registers 4.1.1.2. Restrictions for Pipeline Registers 4.1.1.3. Supported Register Configurations per Operation Modes
4.1.4. Input Cascade for Fixed-point Arithmetic x
4.1.4.1. Dynamic Scanin
4.2. Floating-point Arithmetic x
4.2.1. Configurations for Input, Pipeline, and Output Registers 4.2.2. Chainout Adder
4.2.1. Configurations for Input, Pipeline, and Output Registers x
4.2.1.1. FP32 Operation Modes Supported Register Configurations 4.2.1.2. FP16 Operation Mode Supported Register Configurations
5. Native Fixed Point DSP Agilex FPGA IP References x
5.1. Native Fixed Point DSP Agilex™ FPGA IP Release Information 5.2. Supported Operational Modes 5.3. Maximum Input Data Width for Fixed-point Arithmetic 5.4. Maximum Output Data Width for Fixed-point Arithmetic 5.5. Parameterizing Native Fixed Point DSP IP 5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals 5.7. IP Migration
5.3. Maximum Input Data Width for Fixed-point Arithmetic x
5.3.1. Using Less Than 36-Bit Operand In 18 x 18 Plus 36 Mode Example
5.5. Parameterizing Native Fixed Point DSP IP x
5.5.1. Operation Mode Tab 5.5.2. Input Cascade Tab 5.5.3. Pre-adder Tab 5.5.4. Internal Coefficient Tab 5.5.5. Accumulator/Output Chaining 5.5.6. Pipelining 5.5.7. Clear Signal
5.6. Native Fixed Point DSP Agilex™ FPGA IP Signals x
5.6.1. 9 × 9 Sum of 6 Mode Signals 5.6.2. 16 × 16 Complex Multiplier Mode Signals 5.6.3. 18 × 18 Full Mode Signals 5.6.4. 18 × 18 Sum of Two Mode Signals 5.6.5. 18 × 18 Plus 36 Mode Signals 5.6.6. 18 × 18 Systolic Mode Signals 5.6.7. 27 × 27 Mode Signals
6. Native Floating Point DSP Agilex FPGA IP References x
6.1. Native Floating Point DSP Agilex™ FPGA IP Release Information 6.2. Native Floating Point DSP Agilex™ FPGA IP Supported Operational Modes 6.3. Parameterizing the Native Floating Point DSP Agilex™ FPGA IP 6.4. Native Floating Point DSP Agilex™ FPGA IP Core Signals 6.5. IP Migration
6.3. Parameterizing the Native Floating Point DSP Agilex™ FPGA IP x
6.3.1. General Tab 6.3.2. Registers Tab
6.4. Native Floating Point DSP Agilex™ FPGA IP Core Signals x
6.4.1. FP32 Multiplication Mode Signals 6.4.2. FP32 Addition or Subtraction Mode Signals 6.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals 6.4.4. FP32 Multiplication with Accumulation Mode Signals 6.4.5. FP32 Vector One and Vector Two Modes Signals 6.4.6. Sum of Two FP16 Multiplication Mode Signals 6.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals 6.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals 6.4.9. FP16 Vector One and Vector Two Modes Signals 6.4.10. FP16 Vector Three Mode Signals
7. Native AI Optimized DSP Agilex™ FPGA IP References x
7.1. Native AI Optimized DSP Agilex™ FPGA IP Release Information 7.2. Native AI Optimized DSP Agilex™ FPGA IP Supported Operational Modes 7.3. Parameterizing the Native AI Optimized DSP Agilex™ FPGA IP 7.4. Native AI Optimized DSP Agilex™ FPGA IP Signals 7.5. IP Migration
7.3. Parameterizing the Native AI Optimized DSP Agilex™ FPGA IP x
7.3.1. Operation Mode Tab 7.3.2. Clock Source Enable/Clear Tab
7.4. Native AI Optimized DSP Agilex™ FPGA IP Signals x
7.4.1. Tensor Floating-point Mode Signals 7.4.2. Tensor Fixed-point Mode Signals 7.4.3. Tensor Accumulation Mode Signals
8. Multiply Adder FPGA IP References x
8.1. Multiply Adder FPGA IP Release Information 8.2. Features 8.3. Parameters 8.4. Signals
8.2. Features x
8.2.1. Pre-adder 8.2.2. Systolic Delay Register 8.2.3. Pre-load Constant 8.2.4. Double Accumulator
8.2.1. Pre-adder x
8.2.1.1. Pre-adder Simple Mode 8.2.1.2. Pre-adder Coefficient Mode 8.2.1.3. Pre-adder Input Mode 8.2.1.4. Pre-adder Square Mode 8.2.1.5. Pre-adder Constant Mode
8.3. Parameters x
8.3.1. General Tab 8.3.2. Extra Modes 8.3.3. Multipliers Tab 8.3.4. Preadder Tab 8.3.5. Accumulator Tab 8.3.6. Systolic/Chainout Tab 8.3.7. Pipelining Tab
9. ALTMULT_COMPLEX FPGA IP References x
9.1. ALTMULT_COMPLEX FPGA IP Release Information 9.2. Features 9.3. Parameters 9.4. Signals
10. LPM_MULT FPGA IP References x
10.1. LPM_MULT FPGA IP Release Information 10.2. Features 10.3. Parameters 10.4. Signals
10.3. Parameters x
10.3.1. General Tab 10.3.2. General 2 Tab 10.3.3. Pipelining Tab
11. LPM_DIVIDE (Divider) FPGA IP References x
11.1. LPM_DIVIDE FPGA IP Release Information 11.2. Features 11.3. Verilog HDL Prototype 11.4. VHDL Component Declaration 11.5. VHDL LIBRARY_USE Declaration 11.6. Ports 11.7. Parameters
11.7. Parameters x
11.7.1. General Tab 11.7.2. General1 Tab
1. Agilex™ 3 Variable Precision DSP Blocks Overview
2. Agilex™ 3 Variable Precision DSP Blocks Architecture
3. Agilex™ 3 Variable Precision DSP Blocks Operational Modes
4. Agilex™ 3 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Agilex FPGA IP References
6. Native Floating Point DSP Agilex FPGA IP References
7. Native AI Optimized DSP Agilex™ FPGA IP References
8. Multiply Adder FPGA IP References
9. ALTMULT_COMPLEX FPGA IP References
10. LPM_MULT FPGA IP References
11. LPM_DIVIDE (Divider) FPGA IP References
12. Document Revision History for the Variable Precision DSP Blocks User Guide: Agilex™ 3 FPGAs and SoCs

3.3.2. Side Input Feed Preloading Method

The side input feed preloading method preloads the ten 8-bit weight data and 8-bit shared exponent data into the ping-pong buffers using side_in_1[7:0] and side_in_2[7:0] buses. The preloading process takes 12 cycles to complete preloading for one set of ping-pong buffers. The weight and shared exponent data are preloaded independently even if the DSP blocks are cascaded. This enables the tensor computation to continue using one set of buffers whilst the other set is being pre-loaded. The following figure shows the dataflow for side input feed.

Figure 52. Dataflow for Side Input Feed MethodThe feed paths are highlighted in red in this figure.
Figure 53. Side Input Feed Method Timing Diagrams
Note: SEC1 refers to the shared exponent for column 1 and SEC2 refers to the shared exponent for column 2. BxCy refers to the buffer associated with data_in_x in column y, i.e. B10C2 is the buffer multiplied with data_in_10 in column 2.
  1. The update process starts in cycle 1 by setting load_bb_one or load_bb_two to 1’b1. During this first cycle, computation may continue using the buffer set determined by load_buf_sel.
  2. New shared exponents and weights are loaded during cycles 2 through to cycle 13.
    • Data is loaded in accordance with the pattern in the previous diagram via side_in_2 and side_in_1.
    • Note that cycles 2 and 3 are still required when the shared exponent is not used as in tensor fixed-point mode.
    • During side feed loading, computation can continue using the other set of buffers as determined by the load_buf_sel signal.
    • load_bb_one or load_bb_two should become inactive in cycle 13, one cycle before the last of the data is loaded via side_in_2 and side_in_1.
    • load_bb_one or load_bb_two becomes inactive one cycle before the last data is fed in through side_in_1 and side_in_2.
  3. In cycle 14, the newly loaded buffer content is ready for computation and the load_buf_sel signal can be switched to the new buffer set for computation to continue with the previous set.
Level Two Title