1.1. External Memory Interfaces (EMIF) IP v4.0.0

External Memory Interfaces (EMIF) IP Release Notes: Agilex™ 3 FPGAs and SoCs

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ID 848079

Date 7/07/2025

Version

Public

Table 1. v4.0.0 2025.07.07
Description	Impact
Verified in the Quartus® Prime software v25.1.1.	Provides external memory interface IP for Agilex™ 3 devices. The tables that follow summarize speed and feature support.

Note: This documentation is preliminary and subject to change.

Table 2. Agilex™ 3 C-Series Fabric EMIF/HPS EMIF IP Speed Support Summary
			Max Rate (Mbps/MHz)		-6				-7
Protocol	Category	Subcategory	-6	-7	S	C	T	H	S	C	T	H
LPDDR4	Memory Format	Both Fabric and HPS EMIF - Component	2133/1066 (1R)	2133/1066 (1R)	X	X	X¹	X²	X	X	X¹	X²
LPDDR4	Memory Format	Both Fabric and HPS EMIF - Component	2133/1066 (2R)	2133/1066 (2R)	X	X	X¹	X²	X	X	X¹	X²
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. An empty table cell indicates that the feature is not currently supported. ¹ = Timing is currently preliminary. It will be necessary to recompile designs in future releases. ² = Hardware support is available for M16A packages.

Table 3. Agilex™ 3 C-Series Fabric EMIF IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	S	C	T	H
LPDDR4	Interface Width	1ch x32	X	X	X	X	X
		1ch x16	X	X	X	X	X
		2ch x16	X	X	X	X	X
	Controller	Hard Controller	X	X	X	X	X
	Design Example		X	X	X	X	X
	DBI	Read DBI	X	X	X	X	X
	DBI	Write DBI	X	X	X	X	X
	DM	DM pins	X	X	X	X	X
	Preamble	Read preamble settings
	Preamble	Write preamble settings
	Postamble	Read postamble settings	X	X	X	X	X
	Postamble	Write postamble settings	X	X	X	X	X
	Mainband access mode	Fabric Direct - user clock asychronous to PHY	X	X	X	X	X
	Mainband access mode	Fabric Direct - user clock sychronous to PHY	X	X	X	X	X
	ECC	In-line ECC	X	X	X	X	X
	Debug	EMIF Toolkit	X		X	X	X
	Simulators ¹	VCS ^*
		VSC-MX ^*	X	X
		Modelsim SE ^*	X	X
		Xcelium ^*	X	X
		Riviera-PRO ^*	X	X
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.

Table 4. Agilex™ 3 C-Series HPS EMIF IP Feature Support Summary
Protocol	Category	Sub-Category	Supported?	C	T	H
LPDDR4	Interface Width	1ch x32	X	X	X	X
		1ch x16	X	X	X	X
		2ch x16	X	X	X	X
	Controller	Hard controller	X	X	X	X
	Design Example
	DBI	Read DBI	X	X	X	X
	DBI	Write DBI	X	X	X	X
	DM	DM pins	X	X	X	X
	Preamble	Read preamble settings
	Preamble	Write preamble settings
	Postamble	Read postamble settings	X	X	X	X
	Postamble	Read postamble settings	X	X	X	X
	Mainband access mode	Direct path to HPS	X	X	X	X
	ECC	In-line ECC	X	X	X	X
	Debug	EMIF Toolkit
	Simulators ¹	VCS
		VCS-MX
		Modelsim SE
		Xcelium
		Aldec
Support level key: S = simulation support C = compilation support T = timing support H = hardware support X = supported feature. ¹ = VHDL is not supported.