GTS AXI Multichannel DMA IP for PCI Express* Release Notes

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ID 847491
Date 8/04/2025
Public

1.1. GTS AXI Multichannel DMA IP for PCI Express IP Core v1.1.0

Table 1.  v1.1.0 2025.08.04
Quartus® Prime Version Description Impact
25.1.1 Added support for Gen4 1x8 User Mode (512-bit). You can implement designs up to Gen4 x8 in Agilex™ 5 D-Series FPGAs.
Added the following design example variants:
  • AXI-S Packet Generate/Check
  • AXI-MM DMA
  • AXI-MM BAM EP Memory
  • AXI-MM Traffic Generator/Checker
 You can now evaluate the GTS AXI Multichannel DMA IP for PCI Express through these design examples and accompanying software driver applications.
Level Two Title