Device Configuration User Guide Agilex™ 3 FPGAs and SoCs
ID
847422
Date
5/23/2025
Public
1. Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 Configuration Details
3. Agilex™ 3 Configuration Schemes
4. Including the Reset Release IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 3 Configuration Features
7. Agilex™ 3 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II IP
3.1.7.4. Constraining the Parallel Flash Loader II IP
3.1.7.5. Using the Parallel Flash Loader II IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II IP
3.1.7.3.2. Mapping Parallel Flash Loader II IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II IP Functions
3.1.7.4.1. Parallel Flash Loader II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II IP Recommended Design Constraints for Using CFI Flash
3.1.7.4.4. Parallel Flash Loader II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 3 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
4.1. Understanding the Reset Release IP Requirement
Agilex™ 3 devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Device configuration proceeds in parallel with each Local Sector Manager (LSM) configuring its own sector. Consequently, FPGA registers and core logic do not exit reset at exactly the same time, as has always been the case in previous families.
The continual increases in clock frequency, device size, and design complexity now necessitate a reset strategy that considers the possible effects of slight differences in the release from reset. The Reset Release IP holds a control circuit in reset until the device has fully entered user mode. The Reset Release IP generates an inverted version of the internal INIT_DONE signal, nINIT_DONE for use in your design.
After nINIT_DONE asserts (low), all logic is in user mode and operates normally. You can use the nINIT_DONE signal in one of the following ways:
- To gate an external or internal reset.
- To gate the reset input to the transceiver and I/O PLLs.
- To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers.
- To synchronously drive register reset input ports in your design.
Attention: If you use multiple Reset Release IP instances in your design, the nINIT_DONE signals are driven directly from the same source in SDM.