Device Configuration User Guide Agilex™ 3 FPGAs and SoCs
ID
847422
Date
9/29/2025
Public
1. Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 Configuration Details
3. Agilex™ 3 Configuration Schemes
4. Including the Reset Release IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 3 Configuration Features
7. Agilex™ 3 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
2.1. Agilex™ 3 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS
2.5. Agilex™ 3 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 3 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II IP
3.1.7.4. Constraining the Parallel Flash Loader II IP
3.1.7.5. Using the Parallel Flash Loader II IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II IP
3.1.7.3.2. Mapping Parallel Flash Loader II IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II IP Functions
3.1.7.4.1. Parallel Flash Loader II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II IP Recommended Design Constraints for Using CFI Flash
3.1.7.4.4. Parallel Flash Loader II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 3 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
5.6.5. Adding an Application Image
Complete the following steps to add an application image to flash memory:
- Set up exclusive access to the AS x4 interface and flash memory by running the QSPI_OPEN and QSPI_SET_CS commands in the Tcl Console window. You now have exclusive access to the AS x4 interface and flash until you relinquish access by running the QSPI_CLOSE command. Write the new application image to the flash memory using the QSPI_WRITE command.
- Alternatively, the rsu1.tcl script includes the program_flash function that programs a new application image into flash memory. The following command accomplishes this task:
program_flash new_application_image.rpd 0x03FF0000 1024
The program_flash function takes three arguments:
- The .rpd file to write to flash memory.
- The start address.
- Number of words to write for each QSPI_WRITE command. The QSPI_WRITE supports up to 1024 words per write instruction.
Figure 83. Program New Application Image$ source rsu1.tcl /channels/local/top/master_1 $ program_flash new_application_image.rpd 0x03ff0000 1024 total number of words is 584704 total number of page is 571 total number of sector is 36 reading rpd is completed start writing flash writing flash is completed
- Write the new application image start address to a new image pointer entry in the configuration firmware pointer block (CPB) using the QSPI_WRITE command. Ensure that the new image pointer entry value is 0xFFFFFFFF before initiating the write.
Note: When using HPS to manage RSU, you must update both copies of the Configuration Pointer Block (CPB0 and CPB1) and the sub-partition table (SPT). In a non-HPS case, while updates to both copies of the pointer blocks are mandatory, the updates to the sub-partition table are not required. For more details about the SPT and CPB, refer to Sub-partition Table Layout for the sub-partition table layout and Pointer Block Layout for the pointer block layout.
Based on the example described above, the address offset 0x20 in the CPB0 and CPB1 must point to the start address of the application image. The next new image pointer entry value must be 0xFFFFFFFF before you write the start address of the new application image to the next image pointer entry.
CPB Start Address + 0x20 | Content | Value |
---|---|---|
CPB0 + 0x20 = 0x004A0020 | Current application image pointer entry (highest priority) | 0x004B0000 |
CPB0 + 0x28 = 0x004A0028 | Next image pointer entry | 0xFFFFFFFF |
CPB1 + 0x20 = 0x004A8020 | Current application image pointer entry (highest priority) | 0x004B0000 |
CPB1 + 0x28 = 0x002EC028 | Next image pointer entry | 0xFFFFFFFF |
You can use the QSPI_read function verify that the new image pointer entry value is 0xFFFFFFFF . The QSPI_read function takes in two arguments:
- Start address
- Number of words to read
Figure 84. Verifying that the New Image Pointer entry Value is 0xFFFFFFFF
$ qspi_read 0x004a0020 1 0x004b0000 $ qspi_read 0x004a0028 1 0xffffffff % qspi_read 0x004a8020 1 0x004b0000 % qspi_read 0x004a8028 1 0xffffffff
You can now proceed to write the new application image address to next image entry by using the QSPI_write_one_word function. The QSPI_write_one_word function takes in two arguments:
- Address
- The value of the word
Figure 85. Writing an Address Pointer to the New Image Pointer Entry
% qspi_write_one_word 0x004a0028 0x03FF0000 % qspi_write_one_word 0x004a8028 0x03FF0000
You can now do a QSPI_read function to the next image pointer entry to ensure that it is written with the start address of the desired new application image.
Figure 86. Verifying the Update to the New Image Pointer
% qspi_read 0x004a0028 1 0x03FF0000 % qspi_read 0x004a8028 1 0x03FF0000
Host software can now reconfigure the Agilex™ 3 FPGA with the new application image by asserting the nCONFIG pin. Alternatively, you can power cycle the PCB. After reconfiguration, check the current image address. The expected address is 0x03ff0000. After adding a new image, your application image list includes the newly added application image and the old application image, which is now a secondary image. The newly added application image has the highest priority.
Note: When the remote system update host loads an application image, the decision firmware traverses the image pointer entries in reverse order. The new image has the highest priority when you restart the device.