Device Configuration User Guide Agilex™ 3 FPGAs and SoCs
ID
847422
Date
5/23/2025
Public
1. Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
2. Agilex™ 3 Configuration Details
3. Agilex™ 3 Configuration Schemes
4. Including the Reset Release IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 3 Configuration Features
7. Agilex™ 3 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 3 FPGAs and SoCs
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II IP
3.1.7.4. Constraining the Parallel Flash Loader II IP
3.1.7.5. Using the Parallel Flash Loader II IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II IP
3.1.7.3.2. Mapping Parallel Flash Loader II IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II IP Functions
3.1.7.4.1. Parallel Flash Loader II IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II IP Recommended Design Constraints for Using CFI Flash
3.1.7.4.4. Parallel Flash Loader II IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 3 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
5.4.2.2. Sub-Partition Table Layout
The following table shows the structure of the sub-partition table. The Quartus® Prime Programming File Generator software supports up to 126 partitions. Each sub-partition descriptor is 32 bytes.
Note: The firmware never updates the SPT.
Offset | Size (in bytes) | Description |
---|---|---|
0x000 | 4 | Magic number 0x57713427 |
0x004 | 4 | Version number:
|
0x008 | 4 | Number of entries |
0x00C | 4 | Checksum:
|
0x010 | 16 | Reserved |
0x020 | 32 | Sub-partition Descriptor 1 |
0x040 | 32 | Sub-partition Descriptor 2 |
0xFE0 | 32 | Sub-partition Descriptor 126 |
Starting with Quartus® Prime Pro Edition software version 20.4, the SPT header contains a CRC32 checksum that is computed over the whole SPT. The value of the CRC32 checksum field itself is assumed as zero when the checksum is computed.
The checksum is provided as a convenience so that SPT corruptions can better be detected by HPS software. By default the feature is turned off.
Each 32-byte sub-partition descriptor contains the following information:
Offset | Size | Description |
---|---|---|
0x00 | 16 | Sub-partition name, including a null string terminator |
0x10 | 8 | Sub-partition start offset |
0x18 | 4 | Sub-partition length |
0x1C | 4 | Sub-partition flags |
Two flags are currently defined:
- System flag, if set to 1: Reserved for RSU system. For partition offset value, refer to RSU Image Sub-Partitions Layout.
- Read-only flag, if set to 1: The system protects partition against direct writes.
Note: You can use the read-only flag as an additional information during your API development. Read-only flag=1 indicates the content can only be changed by API from Altera.
The Quartus® Prime Programming File Generator sets these flags as follows at image creation time, then they are not changed afterward:
Partition | System | Read Only |
---|---|---|
BOOT_INFO | 1 | 1 |
FACTORY_IMAGE | 1 | 1 |
SPT0 | 1 | 0 |
SPT1 | 1 | 0 |
CPB0 | 1 | 0 |
CPB1 | 1 | 0 |
P1 | 0 | 0 |
P2 | 0 | 0 |
Note: In order to successfully update SPTs, the HPS software (U-Boot or Linux) must be configured to have a QSPI erase granularity of 32 KB or less. When configured with a coarser erase granularity (like 64 KB for example), the operation fails. All supported flash devices offer erase granularities of 4 KB, 32 KB, and 64 KB, and the default for the current HPS software is 4 KB.