Device Configuration User Guide Agilex™ 3 FPGAs and SoCs

ID 847422
Date 5/23/2025
Public
Document Table of Contents

3.1.7.4.1. Parallel Flash Loader II IP Recommended Design Constraints to FPGA Avalon-ST Pins

Create a pfl_clk clock and a generated AVST_CLK clock

Example below creates a pfl_clk clock running at 50 MHz, supplied by the clk_50m_sysmax input clock.

set pfl_clk_period 20.000
create_clock -name {clk_50m_sysmax} -period $pfl_clk_period [get_ports {clk_50m_sysmax}]
create_generated_clock -name AVST_CLK -source [get_ports {clk_50m_sysmax}] [get_ports {avst_clk}]

Set output delay for Parallel Flash Loader II IP output pins

Example below sets the output delay for the AvST_DATA and AvST_VALID pins.

Setting a false path

You can set the AVST_READY input pin to a false path since this pin is not synchronous to the AVST_CLK clock. The host must synchronize the AVST_READY signal to the AVST_CLK signal using a 2-stage register synchronizer.

set_false_path -from [get_ports {avst_ready}] -to *