GTS Transceiver Dual Simplex Interfaces User Guide

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ID 825853
Date 1/24/2025
Public

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5. Document Revision History for the GTS Transceiver Dual Simplex Interfaces User Guide

Document Version Quartus® Prime Version Changes
2025.01.24 24.3.1 Made the following changes:
  • Added links to the Serial Lite IV and JESD204B user guides in the Introduction chapter.
  • Updated the Supported Protocol IP Combinations for Dual Simplex Mode table in the Overview chapter with JESD204C support information.
  • Updated the Understanding and Planning Dual Simplex Interfaces section with information about the FEC setting in DS mode.
  • Updated the note in Generating the Simplex IP section with GTS JESD204B Intel FPGA IP and GTS Serial Lite IV Intel FPGA IP settings requirements for simplex mode.
  • Updated the Using the Dual Simplex Assignment Editor section with additional step for using a shared clock between the RX simplex and TX simplex modes.
  • Updated the DS_GROUP_0.sv Reset Sequencer and System PLL Ports Interface figure in the Connecting the Dual Simplex IP section.
2024.10.07 24.3 Made the following changes:
  • Added links to the JESD204C user guides in the Introduction chapter.
  • Updated the Supported Protocol IP Combinations for Dual Simplex Mode table in the Overview chapter with JESD204C support information.
  • Updated the note in Generating the Simplex IP section with GTS JESD204C Intel FPGA IP settings requirements for simplex mode.
2024.08.19 24.2 Initial release.
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