GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 9/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating a GTS SDI II Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.5. SDI II Design Example Parameters

Table 7.  SDI II Design Example Tab Parameters
Parameter Value Description
Select Design
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback

Select a design example for generation.

  • Parallel loopback with external VCXO: Parallel loopback design with an external VCXO to synchronize the clock between RX and TX.
  • Parallel loopback without external VCXO: Parallel loopback design utilizes internal PLL on IP to synchronize the clock between RX and TX. The TX PLL operates in fractional mode with 141 MHz as its reference clock frequency.
  • Serial loopback: An internal video pattern generator generates along with TX and transmits to RX. This design allows simple demonstration when you do not have a video source available.

For Agilex 3 designs, only Serial loopback design is available
Enable Dual Simplex Generation On or off

Turn on this option to generate dual simplex necessary files for Quartus® Prime compilation.

Only turn on Enable Dual Simplex generation for Serial loopback with hardware support.
Simulation On or off Turn on this option to generate necessary files for simulation testbench.
Select Simulation Type With PHY or Without PHY

Select Without PHY to generate the testbench with the SDI IP instantiated but without the PHY.

You must select a single rate video standard and turn off Enable dual simplex generation.
Synthesis On

Turn on this option to generate necessary files for Quartus® Prime compilation and hardware demo.
Generate File Format
  • Verilog
  • VHDL
 Select the HDL format for generated design example fileset. Note that the HDL format only affects the generated top level IP files. All the other files, for example testbenches and top level files for hardware demo are in Verilog.
Select Daughter Card Nextera VIDIO 12G-SDI FMC card Select the daughter card for the targeted design example.
Select Board
  • No Development Kit
  • Agilex™ 5 E-Series Modular Development Kit
  • Agilex™ 5 E-Series Premium Development Kit
 Select the board for the targeted design example.
  • No Development Kit: This option excludes hardware aspects for the design example. Select this option if you target on custom development kit and set the pin assignments with the design generated using custom development kit.
  • Agilex™ 5 E-Series Modular Development Kit or Agilex™ 5 E-Series Premium Development Kit: Select this option to target the pin mapping for the development kit. You can change the target device with the Change Target Device parameter if your board revision has a different grade from the default targeted device. All the pins assignment is set accordingly to the development kit.
Change Target Device On or off

Turn on to select different device grade for Altera development kit.
Level Two Title