GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 823543
Date 11/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. GTS SDI II IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. GTS SDI II IP Design Example Quick Start Guide x
1.1. SDI II Design Example Directory Structure 1.2. Generating a GTS SDI II Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the SDI II Design Example in Hardware 1.5. SDI II Design Example Parameters
1.4. Compiling and Testing the SDI II Design Example in Hardware x
1.4.1. Testing in Hardware - Parallel or Serial Loopback
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. SDI II Design Example Signals 2.6. Debugging Feature 2.7. Design Limitations and Known Issues
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. SDI II Design Example Testbench Components 2.4.2. Test Description
2.6. Debugging Feature x
2.6.1. GTS Transceiver Toolkits Debugging Feature
1. GTS SDI II IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
4. Document Revision History for the GTS SDI II IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

2.6.1. GTS Transceiver Toolkits Debugging Feature

Use this feature to debug the GTS transceiver link running on your board. For example, you can use this feature to debug video symbol or alignment lock stable for RX and external SDI link flickering cases for TX. The GTS Transceiver Toolkit Debugging feature is not supported for Agilex™ 5 dual simplex design. Currently, SDI only supports excluded transceiver (Excluded PHY) and non-dual simplex (Non-DS) designs.

To enable the GTS Transceiver Toolkit, follow these steps:

Figure 29. Enable Transceiver Toolkit
  1. Click on Enable Transceiver Toolkit in the Design Example tab under Design Example Options.
  2. After selecting Enable Transceiver Toolkit, you can proceed to generate the design example.
  3. Compile the Design and Program SOF file to the board.
  4. Launch the System Debugging Toolkits (by selecting Tools > System Debugging Tools > System Debugging Toolkits).
  5. Transceiver links are identified automatically and displayed in the Toolkit Explorer.

  6. In the Collection status table, select the pins for the RX and TX channels.

    Figure 30. Pin RX and TX Channels

  7. You can set TX Equalization Parameters in the TX Channel Parameters tab. Load the values by selecting Get Parameters or key in the values by selecting Set Parameters.

    Figure 31. Set TX Equalization Parameters

  8. Check the TX PLL Locked signal status.

    Figure 32. TX PLL Lock Signals for TX Channel

  9. You can set the RX PMA Settings in the RX Channel Parameters tab. Load the values by selecting Refresh Parameters or key in the values by selecting Set Parameters.

    Figure 33. Set RX Equalization Parameters
  10. After setting the value, click on Refresh Parameters to update values of the RX PMA Settings.

  11. Check RX CDR locked to ref clock signal and RX CDR locked to data signal in the RX tab.

    Figure 34. RX CDR Lock Signals for RX Channel
  12. Repeat tuning the parameters until the video lock signal becomes stable for RX and no flickering issues for TX.
  13. Hard PRBS generator in TX and Hard PRBS checker in RX are only supported in Static Rate Design. Other designs support will be enabled in future releases.
  14. To enable the Internal PRBS checker, follow these steps:
    1. Hardware connection—connect RX to TX loopback.
    2. In the RX top-level file, uncomment out the lines and comment out rst_trig_rst for sdi_rx_phy_inst|i_rx_reset.
    3. Recompile the design again and repeat step 4 to step 13.

    4. Before running the PRBS checker, ensure the Loopback mode in the RX channel is turned Off.

      Figure 35. Loopback Mode in RX Channel
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