AXI Multichannel DMA IP for PCI Express* User Guide

ID 817911
Date 8/11/2025
Public
Document Table of Contents

2.2. IP Features

The AXI MCDMA IP includes the functionality of the Avalon MCDMA IP, with the primary difference lying in the added support for PCIe Gen5 1x16 and transitioning from Avalon to AXI interface protocol.

AXI MCDMA IP Features

  • Interfaces with AXI Streaming FPGA IP for PCI Express in Agilex 7 I-Series with R-Tile variants.
  • Supports PCIe Gen3/4/5 1x16, 1x8, and 1x4 Root Port and Endpoint modes.
    Note:
    • To generate 1x8, or 1x4 IP, create a quartus.ini file in the project directory with the content: ini_guard=on.
    • 2x8 mode is supported for the design example only.
  • User interface bandwidth: 256/512/1024-bits @ up to 500 MHz