5.3.1. PCIe AXI-ST TX Interface (ss_tx_st)
5.3.2. PCIe AXI-ST RX Interface (ss_rx_st)
5.3.3. Control and Status Register Interface (ss_csr_lite)
5.3.4. Flow Control Credit Interface
5.3.5. Configuration Intercept Interface (CII)
5.3.6. Completion Timeout Interface (ss_cplto)
5.3.7. Function Level Reset Interface
5.3.8. Control Shadow Interface (ss_ctrlshadow)
5.4.1. H2D AXI-ST Source (h2d_st_initatr)
5.4.2. D2H AXI-ST Sink (d2h_st_respndr)
5.4.3. H2D/D2H AXI-MM Master
5.4.4. BAM AXI-MM Master (bam_mm_initatr)
5.4.5. BAS AXI-MM Slave (bas_mm_respndr)
5.4.6. PIO AXI-Lite Master (pio_lite_initiatr)
5.4.7. HIP Reconfig AXI-Lite Slave (user_csr_lite)
5.4.8. User Event MSI-X (user_msix)
5.4.9. User Event MSI (user_msi)
5.4.10. User Function Level Reset (user_flr)
5.4.11. User Configuration Intercept Interface - EP Only
5.4.12. Configuration Slave (cs_lite_respndr) - RP Only
2.2.2. Endpoint Mode Features
- Supports 2048 DMA channels (Maximum 512 channels per Function)
- H2D/D2H DMA data transfer via AXI-ST or AXI-MM interface
- Integrated MSI-X for DMA operation and User MSI-X for user applications
- SR-IOV support with 8 PFs and 2048 VFs
- 10-bit tag support
- Completion reordering
- Completion timeout
- User Function Level Reset
- 64-bit Metadata
- User mode and supported user interfaces
- Multichannel DMA
- H2D AXI-ST source
- D2H AXI-ST sink
- H2D/D2H AXI-MM master
- PIO AXI-Lite master
- User MSI-X
- User FLR
- Bursting Master
- BAM AXI-MM master
- Bursting Slave
- BAM AXI-MM slave
- User MSI
- BAM + BAS
- BAM AXI-MM master
- BAS AXI-MM slave
- User MSI
- BAM + MCDMA
- BAM AXI-MM master
- H2D AXI-ST source
- D2H AXI-ST sink
- H2D/D2H AXI-MM master
- User FLR
- User MSI-X
- BAM + BAS + MCDMA
- BAM AXI-MM master
- BAS AXI-MM slave
- H2D AXI-ST source
- D2H AXI-ST sink
- H2D/D2H AXI-MM master
- User FLR
- User MSI-X
- Multichannel DMA
- Optional User Interfaces
- Hard IP Reconfiguration interface
- User Configuration Intercept interface